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A simple 6502 homebrew computer needs a CPU, writable RAM, and ROM containing startup code. But those three functional chips do not always make a literal three-package build: many designs also need a separate address-decoder IC. Unless a complete schematic proves otherwise for your exact parts, treat “three-IC” as the CPU/RAM/ROM core and count decoder logic separately.
The essential design rule is to map ROM where the 65C02 reads its reset vector, and ensure only the intended device drives the data bus during each read. Build and verify the clock, reset, ROM, and RAM in stages before adding peripherals.
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What parts do you need?
A practical starter design uses a 65C02-family processor, SRAM, and EEPROM or other suitable ROM. The part numbers matter: “6502” can refer to different processor variants, and memory devices differ in pinout, voltage, timing, capacity, and chip-select polarity.
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| Part | Role | Design considerations |
|---|---|---|
| 65C02 CPU | Executes instructions and controls the address and data buses. | Check the exact part’s package, pinout, supply range, speed grade, and electrical requirements. The WDC W65C02S datasheet dated February 16, 2024 is the authority for that specific processor: W65C02S datasheet. |
| SRAM | Holds writable memory for zero page, stack, variables, and program data. | A documented design uses a 62256, a 32K × 8 SRAM. A design need not map all of a chip’s capacity; decoder logic determines which address range is selected. See the Stackable 6502 project. |
| EEPROM or other ROM | Stores startup code and the reset vector. | A documented build uses a 28C256; another maps an 8 KiB EEPROM at $E000–$FFFF. Match the programmed image and its placement to the decoder and memory map. See the Crab Apple project. |
| Address-decoding logic | Selects RAM, ROM, and any memory-mapped peripherals according to the address and control signals. | A documented simple design uses a 74LS00 quad NAND gate; a programmable logic device can support more flexible maps. Either is an additional IC package unless a verified design implements the required selects another way. See the Stackable 6502 project. |
| Support components | Provide power, clock, reset, wiring, and ROM programming. | Plan for a regulated supply compatible with every selected chip, local bypass capacitors, a clock source, reset circuit or switch, prototyping board, and a way to program the EEPROM. Use the components’ datasheets for exact voltage, capacitance, timing, and programming requirements. |
The W65C02S has a 16-bit address bus and an 8-bit data bus, giving it 65,536 bytes of address space. Its datasheet specifies several voltage options, including 5.0 V ±5%; that is not a universal supply requirement for every 6502-family processor. Confirm that the CPU, RAM, ROM, and logic all support the same actual rail.
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What does “three-IC” mean in practice?
Count packages, not functions. A CPU, SRAM, and ROM are three ICs, but a design that uses a separate 74LS00 for address decoding has at least four packages. A true three-package design needs a complete schematic showing how valid, non-overlapping chip selects are produced with the chosen devices. Do not assume that a project using three core chips is a literal three-IC circuit.
Before wiring, verify the active-high or active-low polarity of every memory enable and output-enable pin in the exact device datasheets. During a read, the selected device may drive D0–D7; any unselected device must leave the bus alone. During a write, SRAM should accept data only for its intended addresses, while ROM output remains disabled.
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Choose a memory map that matches the decoder and ROM image
The CPU presents addresses on A0–A15, transfers bytes on D0–D7, and uses RWB to distinguish reads from writes. The decoder translates the address and control state into device selects. The following are two documented choices, not a universal standard:
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| Example | RAM | ROM | Other mapping |
|---|---|---|---|
| Stackable 6502 | $0000–$3FFF (16 KiB selected) | $8000–$FFFF (32 KiB) | ACIA at $5000–$5FFF; VIA at $6000–$6FFF; the project warns that $7000–$7FFF conflicts. Project details. |
| Crab Apple | $0000–$7FFF (32 KiB) | $E000–$FFFF (8 KiB ROM image region) | UART occupies $8000–$DFFF in its loosely decoded implementation. Project details. |
For the W65C02S, the reset vector occupies $FFFC (low byte) and $FFFD (high byte). The ROM must be selected at both locations, and those bytes must point to the program’s actual entry address. The decoder, ROM image offset, and chosen map must therefore agree. A valid vector alone is not enough if the ROM is not visible at those addresses.
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Wire and bring up the computer one subsystem at a time
- Plan from exact part numbers. Draw the memory map and make a truth table for RAM and ROM selection, including relevant address and read/write conditions. Check the polarity of every enable pin against the exact chip datasheet; do not wire from a generic “6502” pinout or assume different memories use the same logic.
- Verify power before inserting ICs. Check supply polarity, regulated voltage, and ground continuity. Fit local bypass capacitors as required by the selected devices. One hardware guide suggests 0.1 μF at each IC and bulk capacitance at the supply entry as common practice, but confirm what suits your parts and board in the guide.
- Establish the clock and reset. The W65C02S datasheet recommends an external oscillator for PHI2. Hold RESB low until VDD reaches operating voltage and keep it low for at least two clock cycles; then release reset cleanly. These requirements apply to the W65C02S—check the datasheet for whichever processor you use.
- Prove CPU-to-ROM fetches. Program a small known image with a reset vector that points into mapped ROM. After reset, check that the CPU accesses the expected ROM addresses. Keep peripherals out of the initial test so they cannot add bus or decode faults.
- Add SRAM and check it. Test reads and writes at representative addresses, including low-page and stack-region locations. Look for swapped address or data lines, unintended aliases, and overlapping selects. Choose test addresses based on your map; no single pattern proves every wiring configuration.
- Add one input or output path. Once the memory core works, add a VIA for parallel I/O or an ACIA or other serial solution for terminal interaction. Documented projects also show serial and LCD/VIA expansions: Mike’s 6502 I/O project and HB6502 Homebrew.
Diagnose common bring-up failures
- No meaningful address activity after reset: Check power and ground, PHI2, RESB polarity and timing, the BE state, and whether the bytes at $FFFC–$FFFD point into ROM that is actually mapped there.
- Repeated or mirrored addresses: Check continuity on A0–A15, assumed memory capacity, and decoder inputs. If upper address bits are intentionally unused, multiple addresses may select the same physical memory location.
- Incorrect or unstable reads: Confirm that only one device drives D0–D7 for a read, RWB is connected correctly, ROM is enabled at the reset vector, and the selected parts meet the timing requirements at the clock speed.
- RAM writes do not persist: Check that SRAM chip select and write enable are asserted for the intended writes. EEPROM is not a substitute for writable SRAM in normal program operation.
- The program begins at the wrong address: Check the ROM image offset and map boundaries, then inspect the reset-vector bytes in little-endian order: the low byte at $FFFC, followed by the high byte at $FFFD. In the Crab Apple example, the image is for $E000–$FFFF.
Make the design trade-offs deliberately
- Simple decoding versus address-space flexibility: A small gate-based decoder can be easier to follow but may leave unused address ranges or constrain the map. A PLD can provide more flexible mapping, at the cost of another device and a programming step.
- Clock choice versus ease of diagnosis: An adjustable clock can help when debugging; a fixed oscillator is straightforward once the design is stable. Projects include examples around 1 MHz and 1.8432 MHz, but these are project choices, not a safe universal target. Maximum speed depends on the timing limits of every connected part.
- First visible milestone: A terminal over serial or a simple LED output can demonstrate progress; a VIA can support parallel devices such as an LCD. Add only one path after the core works so a peripheral fault does not obscure a CPU, memory, or decode problem.
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