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What you need
- An FPGA board and its design tool (Vivado, Quartus/Altera, Radiant, or the applicable vendor flow).
- A documented USB-UART bridge, either built into the board or an external 3.3-V-compatible adapter.
- A terminal program such as PuTTY, Tera Term, minicom,
screen, orpicocom. - Optional: an oscilloscope or logic analyzer for checking bit timing and pin routing.
Start by identifying the FPGA family, board revision, clock frequency, I/O voltage, and whether the board USB connector is connected to FPGA fabric. Some USB connectors provide only power, programming, JTAG, or a separate processor connection.
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UART wiring: TX, RX, and ground
What UART means
UART is an asynchronous, serial protocol. There is no shared clock wire; both ends agree on a baud rate and character format. Separate transmit and receive wires normally provide full-duplex communication. A typical 8N1 frame is:
Idle Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Idle
1 0 least-significant bit first 1 1UART describes framing and bit timing, not a connector or voltage standard. “TTL serial,” “RS-232,” and “USB serial” are often used loosely, but they are not interchangeable.
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Logic-level connection
FPGA TX -> adapter RX
FPGA RX <- adapter TX
FPGA GND -- adapter GNDCheck whether the FPGA bank and adapter use 1.8 V, 2.5 V, or 3.3 V signaling. A 5-V adapter can damage lower-voltage FPGA I/O; “3.3-V safe” must be explicit in the adapter documentation. TX always connects to the other device’s RX, and a shared ground is required for a single-ended logic link.
USB-UART bridge
A bridge appears to the computer as a virtual serial port and presents logic-level TX/RX to the FPGA. Chipset drivers, connector wiring, voltage, and maximum baud rate vary. Inspect the board schematic or master constraints file instead of assuming that every USB connector exposes UART.
RS-232 is a separate electrical layer
Do not connect an FPGA GPIO directly to a true RS-232 connector. RS-232 uses different voltage levels and polarity. Use a transceiver such as a MAX3232-family device:
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FPGA UART logic -> USB-UART bridge -> USB connectorIntel’s documentation warns that ordinary FPGA I/O buffers do not meet RS-232 voltage requirements and calls for external level shifting: RS-232 interface guidance.
Custom RTL or vendor IP?
| Choice | Best when | Trade-offs |
|---|---|---|
| Custom RTL | Simple debug output, loopback, no processor bus, portability, or learning | You must verify timing, reset, synchronization, errors, and buffering |
| Vendor IP | AXI, Avalon, or APB systems; processors, drivers, interrupts, and FIFO registers | Generated files, vendor lock-in, and tool-version sensitivity |
| External bridge | PC connectivity for boards without an onboard bridge | Voltage, pinout, driver, and routing must match |
| JTAG debug bridge | Vendor-specific debug workflows without a physical UART cable | Not a generic UART and usually tied to vendor tools |
AMD/Xilinx
AMD AXI UART Lite is an AXI4-Lite soft IP core integrated with Vivado/EDK for supported AMD/Xilinx families. Its product guide is at PG142. The usual connection is UART Lite → AXI4-Lite interconnect → MicroBlaze or Zynq processing system. Configure the AXI clock, baud rate, data width, parity, address, constraints, and (if needed) interrupt. AMD lists examples from 9,600 through 921,600 baud, subject to clock and tolerance limits: baud-rate guidance. The driver documentation describes 16-byte transmit and receive FIFOs and build-time configuration characteristics: UART Lite API.
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- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
Altera/Intel
An Altera design commonly connects UART IP through Avalon-MM to a Nios processor or custom Avalon master. Current product and documentation entry points are altera.com and docs.altera.com; menu names depend on the Quartus/Altera edition. A reference-design example is available in Intel’s archive at Cyclone V UART RS-232 design.
Lattice
Lattice’s UART IP uses APB, supports optional 16-word TX/RX FIFOs, and is included at no additional cost with Radiant. Its register behavior resembles an NS16450 but is not source-code compatible. See the current Lattice UART IP manual.
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Define the FPGA-side interface
A reusable block should expose a system interface rather than raw state-machine signals. A streaming interface is:
tx_data tx_valid tx_ready
rx_data rx_valid rx_readyFor a small educational block, use tx_start, tx_busy, tx_data[7:0], rx_data[7:0], rx_valid, and rx_error. tx_ready prevents a producer from changing data mid-frame. A one-cycle rx_valid without backpressure or a FIFO can lose a byte when the consumer is busy.
Calculate baud timing
For an integer divider, use:
CLKS_PER_BIT = round(FCLK / BAUD)At 50 MHz and 115,200 baud, 50,000,000 / 115,200 = 434.0278, so CLKS_PER_BIT = 434. The generated rate is 50,000,000 / 434 = approximately 115,207.4 baud, an error of about +0.0064%. At 100 MHz, use 868 clocks per bit, producing approximately 115,207.4 baud.
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Divider rounding, independent clock errors, frame length, and sampling position determine the tolerance. If the clock does not divide cleanly, a fractional accumulator (numerically controlled oscillator) distributes timing error more evenly than a fixed rounded count. With 16× oversampling at 50 MHz, the sample interval is 50,000,000 / (115,200 × 16) ≈ 27.1267 clocks; a fractional tick avoids the accumulated error from always using 27.
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For a recommended parameter set:
parameter int CLOCK_HZ = 50_000_000;
parameter int BAUD_RATE = 115_200;
parameter int DATA_BITS = 8;
parameter bit PARITY_ENABLE = 0;
parameter bit PARITY_ODD = 0;
parameter int STOP_BITS = 1;
parameter int FIFO_DEPTH = 16;Implement the transmitter
State sequence
- Wait in
TX_IDLEfor a byte and request. - Drive TX low for one bit period (
TX_START). - Send data least-significant bit first (
TX_DATA). - Send parity if enabled (
TX_PARITY). - Drive TX high for the stop period (
TX_STOP). - Return to idle and assert ready only after the stop bit is complete.
UART idle is high. Shift the transmit register only at bit-period boundaries, expose busy or ready, and hold TX high during reset or immediately after reset. Never allow the producer to modify the active frame.
Implement the receiver
- Pass the asynchronous RX pin through at least two flip-flops clocked by the FPGA clock.
- Detect a falling transition that may be a start bit.
- Wait about half a bit period and confirm RX is still low; otherwise reject a false start.
- Sample each data bit near its center, assembling bits least-significant first.
- Check parity when enabled and verify that the stop bit is high.
- Pulse
rx_validor write the byte to an RX FIFO, reporting any error.
The synchronizer reduces metastability risk; it does not correct baud mismatch or provide buffering. A basic receiver waits CLKS_PER_BIT/2 after start detection, then samples every CLKS_PER_BIT. A 16× design can sample around the eighth oversample and use three-point or majority voting around the center.
Error signals
- Parity error: received parity disagrees with the selected even or odd rule.
- Framing error: the expected stop bit is not high.
- Overrun: a new byte arrives before the previous byte is consumed.
- Break: optional indication that RX stayed low longer than a normal frame.
Parity detects some errors but cannot correct data and can miss an even number of bit errors.
Add FIFOs and system integration
A one-byte register is suitable for a controlled loopback, not for an unpredictable processor or stream. Add a TX FIFO for bursts and an RX FIFO to absorb characters while software or logic is busy. Expose empty, full, almost-empty, almost-full, and overflow status, and define whether an overflow drops the newest or oldest data. AMD UART Lite provides 16-byte TX and RX FIFOs; Lattice offers optional 16-word FIFOs in FIFO mode.
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Processor systems typically use AXI4-Lite (AMD), Avalon-MM (Altera), or APB (Lattice), with polling or interrupts. Keep the UART’s framing engine separate from the bus wrapper so the same RTL can serve a streaming design.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Add FPGA pin constraints
Pin numbers are board- and package-specific. Obtain them from the board schematic or master constraints file; never copy placeholder pins between boards. A generic XDC example is:
set_property PACKAGE_PIN <TX_PIN> [get_ports uart_tx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_tx]
set_property PACKAGE_PIN <RX_PIN> [get_ports uart_rx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rx]In Quartus/Altera, assign the package pins and I/O standard in the project’s pin planner or QSF constraints. Confirm bank voltage, level shifters, multiplexers, and whether the onboard bridge is actually routed to those ports. Synthesize and check timing before programming.
Configure and test a terminal
Use matching settings at both ends:
Baud: 115200
Data: 8 bits
Parity: None
Stop: 1
Flow: NoneFor a deterministic first test, transmit UART OKrn repeatedly, then send a character from the terminal and echo it in the FPGA. This proves the clock, divider, TX path, wiring, RX sampling, and return path without introducing a command protocol.
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Example host commands
screen /dev/ttyUSB0 115200
picocom -b 115200 /dev/ttyUSB0
stty -F /dev/ttyUSB0 115200 cs8 -cstopb -parenb -ixon -ixoffDevice names vary. Windows may assign a port such as COM5. A Python test using pyserial is:
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import serial
with serial.Serial(
"/dev/ttyUSB0",
baudrate=115200,
bytesize=serial.EIGHTBITS,
parity=serial.PARITY_NONE,
stopbits=serial.STOPBITS_ONE,
timeout=1,
) as port:
port.write(b"hello FPGArn")
print(port.readline())At 8N1, each payload byte consumes 10 serial bits, so the theoretical rate at 115,200 baud is 11,520 payload bytes per second before delays, FIFO limits, and protocol overhead. A logic analyzer can confirm one start bit, eight data bits, one stop bit, and approximately 8.68 microseconds per bit.
Troubleshoot failures
Nothing appears
- Confirm the FPGA is configured and TX leaves reset.
- Verify the constrained pin and I/O standard.
- Check that the USB port is a UART path, not only JTAG or power.
- Cross TX and RX and connect ground.
- Select the correct COM or
/dev/tty*device. - Match baud, format, and flow control.
- Confirm the RTL clock-frequency parameter matches the hardware clock.
Garbled characters
Check clock frequency, divider rounding, host format, ground, voltage compatibility, and center sampling. Excessive clock mismatch becomes more visible on long frames.
Lost or unreliable received data
Verify the two-flop synchronizer, start-bit validation, fractional timing (if needed), reset release, and that the consumer handles rx_valid. Add an RX FIFO when software polling or downstream logic can pause.
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Simulation often assumes ideal timing and ignores board routing. Recheck constraints, voltage levels, bridge routing, asynchronous-input synchronization, and reset. An integrated or external logic analyzer distinguishes an RTL problem from a pin, adapter, or terminal problem.
RS-232 damage risk
Never attach FPGA GPIO directly to a true RS-232 port; use the specified transceiver and protection circuitry.
Quick Recap
When UART is the wrong interface
- SPI: short, synchronous, higher-speed board links.
- I²C: low-speed multidrop control.
- RS-485: longer differential and multidrop links.
- CAN: robust industrial or automotive messaging.
- Ethernet: networked or high-throughput systems.
- USB: native USB host or device integration.
Final design checklist
- Clock frequency and baud calculation are correct.
- TX and RX are crossed and ground is shared.
- Voltage levels and I/O standards are compatible.
- RX uses a synchronizer, validated start bit, and center sampling.
- TX exposes busy/ready and holds its frame stable.
- FIFO or backpressure protects traffic bursts.
- Framing, parity, and overrun errors are visible.
- Board-specific pins and routing are verified.
- Fixed transmit text and an echo test pass on hardware.
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