A switched-capacitor filter uses a clock to move small packets of charge between circuit nodes. Averaged over many clock cycles, that transfer behaves like current through a resistor, so changing the clock can change the filter’s cutoff without changing its capacitors. The resistor analogy is useful—but incomplete: the circuit samples its input, so aliasing, clock-related ripple, and switching noise can matter.
What a switched-capacitor filter does
A continuous-time RC filter uses a resistor and capacitor to shape a signal. A switched-capacitor filter can perform a similar job by repeatedly switching a capacitor between nodes. Rather than allowing charge to flow continuously through a physical resistor, it samples a voltage and transfers charge in clocked steps.
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The small capacitor that performs the transfer is often called the flying capacitor. In one clock phase it is connected so it acquires charge related to a voltage difference. In the next phase, the connections change and it transfers charge to another node. The phases are non-overlapping: one switching interval ends before the other begins. This sequence allows the circuit to move charge in a controlled way.
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The transfer is not literally a resistor, and the instantaneous current is not smooth. The useful approximation is an average over repeated cycles. It explains why clock frequency influences the circuit’s effective resistance and, in turn, its filter response.
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How charge transfer creates an equivalent resistance
One cycle moves a charge packet
For a capacitor C experiencing a voltage difference ΔV, the charge associated with that voltage change is approximately:
ΔQ = C · ΔV
If the circuit transfers such a charge packet once per clock cycle at frequency fCLK, then the average current is:
I = ΔQ · fCLK
Substituting the charge relation gives an average current proportional to both capacitance and clock frequency. For a fixed voltage difference, increasing either one increases the charge transferred per second.
The resistor analogy
For a resistor, Ohm’s law relates current to voltage difference: I = ΔV/R. Equating that relationship with the switched-capacitor average-current model gives the idealized equivalent resistance:
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Req = 1 / (C · fCLK)
This relation is an averaged model of the charge-transfer process, not a claim that a physical resistor is present. It also shows the key direction: with capacitance fixed, a higher clock frequency means a lower equivalent resistance. A lower clock means a higher equivalent resistance.
The current in the actual switched circuit arrives in pulses, and its behavior is sampled-data rather than perfectly continuous. The equivalent-resistance model is therefore useful for understanding average behavior and deriving a basic cutoff relationship, but it does not by itself describe aliasing, clock feedthrough, charge injection, or ripple.
How the clock sets cutoff frequency
First-order switched-capacitor low-pass example
Consider the stated first-order topology: a switched capacitor C1 replaces the resistor, and capacitor C2 is connected at the output. For an ordinary first-order RC low-pass, the 3 dB cutoff is:
f3dB = 1 / (2πR C)
Substitute the switched-capacitor equivalent resistance Req = 1/(C1 · fCLK) and use C2 as the filter capacitor. The result is:
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f3dB = (C1 · fCLK) / (2πC2)
This equation applies to that first-order arrangement. If the capacitor values remain fixed, doubling the clock doubles the calculated cutoff. At a fixed clock, increasing C1 relative to C2 raises the cutoff; increasing C2 relative to C1 lowers it.
For example, if a design’s clock is changed from fCLK to 2fCLK while C1 and C2 stay the same, the equation predicts twice the original cutoff. This is a direct consequence of the model, not a measured result or a guarantee about every filter IC.
Why an IC may use a different clock-to-cutoff ratio
Commercial switched-capacitor filter ICs can use multi-pole internal architectures. Their specified clock-to-cutoff ratio is determined by the device, so the simple first-order equation should not be used as a substitute for a datasheet’s ratio, clock limits, or response information.
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What happens during a clock cycle
- First phase—sample: The switching network connects the flying capacitor to a voltage so that it acquires charge associated with the voltage difference.
- Phase transition: The first connection is released before the next phase is active. The non-overlap prevents the phases from being active simultaneously.
- Second phase—transfer: The switching network connects the capacitor to another node, moving charge into or out of that node.
- Repeat: The cycle runs at fCLK. The repeated charge packets produce an average transfer that can be modeled as a resistor-like current.
In a filter, the resulting charge flow interacts with the other capacitors and circuitry to shape the signal. The clock is therefore part of the filtering mechanism, not merely a timing signal that can be ignored after setup.
Why sampling means aliasing can matter
A switched-capacitor filter samples its input. As a result, input energy above half the clock frequency can alias into lower frequencies. Aliasing can make out-of-band input content appear as misleading in-band content; the filter’s nominal cutoff alone does not establish that a signal is protected from this effect.
Whether an input RC filter is needed depends on the signal spectrum and the system around the switched-capacitor stage. A simple passive low-pass can attenuate unwanted high-frequency components before they reach the sampling circuit. The appropriate attenuation and component values depend on the application; no single input filter or cutoff is established for every design.
When evaluating a specific IC, consider the clock frequency relative to the signal bandwidth and examine the device’s stated input bandwidth and clock limits. If appreciable unwanted energy lies above half the clock rate, assess whether it needs attenuation before sampling. Do not assume that a post-filter or a low nominal corner eliminates aliasing that has already occurred at the input.
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Clock-related artifacts and practical limitations
- Clock-rate steps or ripple: Because charge moves in discrete events, output transitions may show clock-rate steps or ripple. The amount depends on the circuit and application.
- Charge injection and broadband noise: Switching can inject charge into the signal path. Texas Instruments’ October 2022 application note, The Davies Sinusoidal Generator (SBOA550), states: “The primary drawback to switched capacitor type filters is the tendency to inject broadband noise into the output due the charge injection of the analog switches involved.” That warning identifies a possible mechanism, not a noise measurement for every device.
- Clock phase jitter: Variations in clock timing can contribute noise or distortion. The significance depends on the clock and the particular signal and filter.
- Response and noise are device-specific: Pole count, response shape, Q, input bandwidth, clock limits, and noise should be checked for the actual part. The idealized resistance equation does not specify those properties.
Output filtering may be relevant if clock-related transitions or ripple affect the next stage, but it should be considered alongside the device’s response and the system’s signal requirements. Filtering the output is not a substitute for addressing input aliasing.
Switched-capacitor versus continuous-time RC filters
| Design consideration | Switched-capacitor approach | Continuous-time RC approach |
|---|---|---|
| Cutoff setting | Set by clock and capacitor ratio in the idealized first-order example; a commercial IC uses its specified clock-to-cutoff relationship. | Set by resistance and capacitance in the RC network. |
| Tuning | Changing the clock can tune cutoff without changing external RC values. | Changing cutoff generally means changing resistance, capacitance, or both. |
| Matching and repeatability | Integrated capacitor matching can improve repeatability compared with relying on absolute resistor values. Analog Devices’ 2005 article gives device-specific examples: 0.1% integrated component matching, 0.2% corner-frequency accuracy for the MAX7490, and 10 ppm/°C drift. These figures are not universal switched-capacitor specifications. | Depends on the components and implementation; the available sources do not establish a general accuracy figure for continuous-time RC filters. |
| Sampling effects | Sampling means aliasing risk must be considered relative to clock frequency and input spectrum. | The switched-capacitor sampling mechanism described here is not present, so this particular clock-related aliasing concern does not apply in the same way. |
| Switching artifacts | Clock ripple, charge injection, and jitter-related noise or distortion may matter. | No switched-capacitor clock artifacts are inherent to the resistor-capacitor network. |
| When it can fit | Useful when compact filtering and accurately clock-tunable cutoff are valuable, subject to the device’s limitations. | May be preferable when sampling artifacts or DC precision dominate the design choice. |
Neither approach is automatically better. The relevant decision is whether clock-based tuning and capacitor matching are worth accounting for sampling, switching artifacts, and the device’s particular constraints.
A practical design and selection workflow
- Define the signal and target response. Establish the signal bandwidth and desired cutoff, and decide what response shape and Q the application requires. A first-order equation does not define the response of a multi-pole device.
- Choose the appropriate model. For the first-order topology described above, use f3dB = (C1 · fCLK)/(2πC2). For a commercial IC, use its specified clock-to-cutoff ratio and device documentation instead.
- Check clock and signal limits. Confirm that the desired cutoff and chosen clock are within the part’s stated clock limits and cutoff range. Compare the clock to the signal bandwidth, and consider input energy above half the clock frequency.
- Assess input conditioning. If the input spectrum includes unwanted high-frequency content that could alias, determine whether a passive input low-pass is needed. Choose it for the system’s signal spectrum rather than assuming one generic value.
- Check non-ideal behavior. Review response/Q, noise, charge injection, clock feedthrough or ripple, and sensitivity to clock phase jitter. Decide whether the resulting behavior is acceptable for the signal and following circuitry.
- Consider output conditioning and DC needs. Determine whether clock-related output steps need attenuation and whether the application’s DC precision requirements favor a continuous-time implementation instead.
- Verify the exact part and operating conditions. Confirm lifecycle, clock specifications, electrical compatibility, and availability from current manufacturer information. A nominal ratio or historical example does not establish present stock or suitability for a particular circuit.
Reading the numbers without overgeneralizing
The equivalent resistance and first-order cutoff equations are circuit models. They explain how capacitance and clock rate interact in the stated arrangement. A device’s actual clock-to-cutoff ratio may differ because its internal filter topology is not that simple network.
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