High Bandwidth Memory (HBM) is made by building DRAM dies, forming through-silicon vias (TSVs) that carry signals between stacked dies, then thinning, bonding, molding and testing the stack. Lithography defines where features such as TSV openings and package wiring go; etching, deposition, plating and polishing turn those patterns into physical electrical connections. The sequence below follows a process explained by SK hynix in 2023, not a universal recipe: manufacturers and HBM generations can differ.
What HBM manufacturing has to accomplish
A conventional memory die places its circuitry across a relatively broad silicon surface. HBM combines multiple DRAM dies vertically, with TSVs providing paths for signals through the silicon and connections between layers. This arrangement supports a high-bandwidth memory stack in a compact package, but it also makes the manufacturing task more than simply producing smaller memory chips: the dies must be connected, thinned, aligned, bonded and kept within package and thermal constraints.
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SK hynix’s October 5, 2023 back-end process explainer describes one route: a via-middle flow in which CMOS transistors are formed first, TSVs are constructed before back-end-of-line (BEOL) metallization is complete, and the dies then proceed through wafer-level packaging operations. It is an example, not evidence that every supplier or generation follows the same order.
How a DRAM wafer becomes a stack
1. Build the DRAM circuitry
Front-end processing forms the memory circuitry on a silicon wafer. In the via-middle example described by SK hynix, CMOS transistors are created before TSV construction. BEOL wiring—the metal interconnect layers that connect devices—is completed later in the flow.
2. Pattern and etch the TSV locations
A hard-mask pattern marks where deep openings should be etched into the silicon. Lithography helps define that pattern; the subsequent etch makes the actual trenches. Placement and fidelity matter because the openings must land where the design requires vertical connections.
3. Insulate and fill the vias
An insulating film, such as oxide, lines each opening so its copper conductor is isolated from the surrounding silicon. A metal barrier layer is added, then copper is electroplated into the trenches. Chemical-mechanical polishing (CMP) removes excess copper from the surface and leaves the wafer ready for later processing.
4. Complete wiring and form bumps
The wafer proceeds through BEOL completion. Bumps are formed to provide connection points between dies or between a die and an interposer. In packaging, photolithography can also pattern redistribution wiring and openings for package connections; plating then builds the conductive features in the patterned areas.
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A temporary adhesive bonds the bumped frontside to a carrier. The carrier supports the wafer during backgrinding, which thins it, and helps manage warpage while backside processing takes place. Backside bumps are then formed and the temporary carrier is debonded. Thinning allows a multilayer stack to fit within package thickness constraints; it also makes mechanical support during processing important.
6. Dice and bond the dies
The processed wafer is diced into core dies, which are stacked onto a base die or base wafer using the prepared bump connections. Depending on the particular process, bonding may use mass reflow or thermocompression. These are manufacturing options, not interchangeable guarantees of the same throughput, yield or thermal result.
7. Mold, finish and test the stack
The stacked wafer is molded and ground to the required package thickness, then diced into known-good stacked dies. SK hynix describes HBM as an example of known-good stacked die prepared for later 2.5D package integration. Testing and package integration are distinct from forming the DRAM circuitry: a working wafer-level die still has to survive stacking and subsequent assembly.
What lithography does—and what it does not do
Lithography transfers a designed pattern into photoresist or a hard-mask layer. That pattern guides later operations: the TSV example uses a patterned hard mask to specify where silicon will be etched, while packaging examples use patterned photoresist to define wiring and other package features before electroplating.
Lithography does not, by itself, make an electrical connection. It defines where a feature should be; etching creates an opening, deposition adds insulating or barrier films, plating supplies metal, and CMP planarizes the surface. The final connection depends on these steps working together and on the resulting features aligning with the design.
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TSVs also consume space in peripheral circuitry. In a 2024 design article, SK hynix said peripheral circuits typically account for 20–30% of memory-product area in the context of explaining this area pressure. That is a company-published general figure, not an independently validated industry-wide measurement. The underlying design trade-off is that via placement and connection count must be balanced against usable die area, memory capacity and package footprint.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why thinning, bonding and thermal management matter
Adding layers increases stack height and makes assembly and heat management more demanding. Thinning helps fit more dies within package constraints, while temporary carriers support thin wafers during backside work. Bumps and bonding join the layers; molding and grinding bring the assembly to its target form. Warpage, alignment and heat dissipation are therefore part of the manufacturing problem alongside transistor fabrication and lithography.
SK hynix’s September 26, 2024 announcement said its 12-layer HBM3E product had 36GB capacity and operated at 9.6 Gbps. The company said the DRAM dies were 40% thinner to fit 12 layers within the thickness of its previous eight-layer product, and reported 10% higher heat-dissipation performance for its Advanced MR-MUF 12-layer HBM3E versus the previous generation. These are dated manufacturer product claims, not independent benchmark results or guarantees for other products.
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The broad logic—fabricate DRAM, create vertical connections, prepare and thin wafers, stack dies, then finish and test the assembly—explains why HBM production combines front-end semiconductor processing with advanced packaging. Exact integration points and recipes are supplier- and generation-specific. Relevant variables include when TSVs are formed, whether stacking is chip-to-chip, chip-to-wafer or wafer-to-wafer, whether bonding uses mass reflow or thermocompression, how temporary carriers are attached and removed, and how underfill or molding is handled.
The available manufacturer descriptions do not establish a neutral head-to-head ranking of those choices, nor do they disclose proprietary lithography recipes, defect density or yield. Samsung’s November 2024 HBM4 page describes a mechanical test vehicle intended for customer preparation, pre-qualification and thermal evaluation; it says the planned production device would use advanced DRAM processing for the core and SF4x (4 nm-class) logic for the base die. Those statements describe a dated prototype announcement, not confirmation of current commercial availability.
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