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A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11ASML’s High-NA EUV scanners keep the 13.5 nm light used by earlier EUV systems but increase the optics’ numerical aperture (NA) from 0.33 to 0.55. ASML specifies 8 nm resolution for the EXE platform, compared with 13 nm for its NXE platform. The higher resolution may let chipmakers print some difficult patterns in fewer exposures. It does not make High-NA a chip-node name, guarantee a particular finished-chip density, or mean every layer should use it. As of October 7, 2026, the clearest reported production-use example is Intel Foundry’s use of High-NA on selected Intel 18A layers for a subset of Core Ultra Series 3 processors.
What “High-NA EUV” means
High-NA refers to a scanner’s numerical aperture: a measure of how much light its optics can collect and focus. EUV means extreme ultraviolet, the light used to expose patterns in the wafer’s resist. ASML’s EXE scanners raise NA to 0.55 from the 0.33 used by its NXE EUV systems. The wavelength remains 13.5 nm; the resolution improvement comes from the optical system, not a shorter wavelength.
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Scanner resolution, transistor density, and a chip’s marketed process-node name describe different things. In its current product information, ASML specifies 8 nm resolution for EXE and 13 nm for NXE. ASML also says the EXE comparison supports features 1.7 times smaller and 2.9 times higher transistor density than NXE. Those are supplier-stated system comparisons, not guaranteed outcomes for every layer, chip design, or manufacturing process.
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How an EUV scanner prints a pattern
- Generate the light. ASML describes firing two CO2 laser pulses at fast-moving tin droplets. The tin vaporizes and produces EUV light at 13.5 nm.
- Guide it with mirrors. EUV is absorbed by air and ordinary glass, so the scanner uses reflective optics rather than conventional transmissive lenses to direct the light.
- Reflect the mask pattern. Light interacts with a reflective patterned mask, also called a reticle. The optics project that pattern onto a silicon wafer coated with light-sensitive resist.
- Develop and transfer the pattern. Exposure changes the resist; development reveals the pattern, which is then used in subsequent etch or deposition steps to form chip structures.
High-NA changes the projection optics and imaging geometry in this chain. It does not replace the mask, resist, development, etch, or other process steps surrounding exposure.
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What changes in the EXE optics—and what the compromise is
Anamorphic imaging keeps traditionally sized reticles
Raising NA required larger projection optics. At the higher incidence angles, a conventional reticle arrangement would create reflectivity and mask-geometry problems. EXE uses anamorphic optics, demagnifying the reticle pattern 4× in one direction and 8× in the other. This enables high-resolution imaging while retaining traditionally sized reticles.
The exposure field is smaller
The anamorphic arrangement gives EXE an exposure field half the size of an NXE field, according to ASML’s 2024 explainer. Covering a wafer therefore requires more exposures. ASML designed faster wafer and reticle stages to address the productivity challenge. In that same 2024 explainer, ASML stated 185 wafers per hour and a roadmap target of 220 wafers per hour in 2025. The target was forward-looking at the time; those figures do not establish current achieved throughput.
Higher NA narrows the process window
Higher resolution comes with less tolerance for focus variation. Imec’s High-NA adoption interview says depth of focus is expected to be 2–3 times smaller than with 0.33-NA EUV. Thinner resist films are one response, but the change also raises demands on overlay, process control, resist behavior, metrology, and integration with etch. The actual process window depends on the layer and manufacturing flow.
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Why a chipmaker might use High-NA on selected layers
The manufacturing case is selective patterning simplification. A sufficiently fine pattern that would otherwise need several patterning steps may be printable in one exposure with High-NA. Fewer patterning steps can reduce cycle time and the number of opportunities for defects, and may make future scaling more economical. ASML and imec describe these as potential benefits; they are not automatic savings for every layer or product.
A fab therefore has to assess more than the scanner’s nominal resolution. The relevant question is whether High-NA improves the complete patterning flow for a particular layer enough to justify its process, qualification, and operating demands.
- Patterning flow: Can one exposure replace multiple patterning steps on this layer, and what changes are needed in etch and the rest of the process?
- Image and process quality: Can the flow meet requirements for overlay, defectivity, focus, resist performance, and measurement?
- Productivity: What throughput is achieved in the relevant production setup? A historical figure or roadmap target is not a current production result.
- Readiness and economics: Is the tool installed, accepted, qualified, or already used in production—and does the layer-specific benefit justify deployment?
High-NA is not a wholesale replacement for other lithography. ASML says NXE EUV and DUV systems will remain in use alongside EXE; different layers and process steps can call for different tools.
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Why the surrounding ecosystem must be ready
A scanner cannot establish a manufacturable pattern by itself. Imec’s readiness work spans advanced resists and underlayers, photomasks, metrology, imaging strategies, optical proximity correction, and integrated patterning and etch. Each part has to work with the optical image and the fab’s process requirements. This is why installation or a resolution specification alone does not demonstrate broad high-volume adoption.
Imec operates a joint ASML-imec High-NA lab in Veldhoven to let chipmakers and suppliers develop and de-risk process integration before inserting it into production fabs. Separately, imec announced on March 18, 2026 that an ASML EXE:5200 had arrived in its Leuven 300 mm cleanroom, with full qualification anticipated by Q4 2026. That announcement set an expectation; it does not verify that qualification was completed by October 7, 2026.
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What adoption had been reported by October 7, 2026
| Date and source | Reported milestone | What it establishes—and what it does not |
|---|---|---|
| July 15, 2026; ASML | Intel Foundry was using a High-NA EUV process option on selected Intel 18A layers to produce a subset of Intel Core Ultra Series 3 processors, code-named Panther Lake. | Evidence of selected-layer production use in a production environment. ASML described it as a readiness milestone and said the work provides data to refine system setup, uptime, and manufacturing implementation. It does not establish High-NA use on every 18A layer or broad adoption across the industry. |
| September 7, 2026; Intel Foundry and ASML | The companies reported more than one million wafers processed to date using High-NA. | A cumulative High-NA processing milestone reported jointly by the companies; it is not necessarily the output of a single scanner and does not by itself demonstrate universal production deployment. |
| March 18, 2026; imec | An ASML EXE:5200 arrived in imec’s Leuven 300 mm cleanroom. Imec anticipated full qualification by Q4 2026. | Evidence of installation and a stated qualification expectation, not confirmation that qualification was complete by the article’s date. |
ASML’s product page describes the EXE platform as supporting high-volume manufacturing in the 2025–2026 timeframe, and imec’s earlier interview gave a similar expected timeframe. These dated expectations are not evidence that all manufacturers or products had moved to High-NA.
EXE High-NA and NXE EUV at a glance
| Characteristic | ASML EXE High-NA | ASML NXE EUV |
|---|---|---|
| Numerical aperture | 0.55 (ASML product information accessed in 2026) | 0.33 (ASML product information accessed in 2026) |
| Specified resolution | 8 nm (ASML specification) | 13 nm (ASML specification) |
| Exposure field | Half the size of NXE’s, according to ASML’s 2024 explainer | Reference field for the comparison; ASML’s cited statement gives the relative size, not an absolute field measurement |
| Reticle imaging | Anamorphic: 4× demagnification in one direction and 8× in the other; preserves traditionally sized reticles | Not stated in the cited comparison |
| Supplier-stated comparison | ASML says EXE can print features 1.7× smaller and support 2.9× higher transistor density than NXE; it also reports 40% more imaging contrast than NXE | Comparison baseline for ASML’s claims; these are not independent measurements or guaranteed chip-level results |
The relative field size and EXE’s stage response are the useful operational context for the optical comparison: resolution gains do not remove the need to manage wafer coverage and throughput.
What the evidence does not establish
As of October 7, 2026, the reported Intel example supports selected-layer production use, while the other cited milestones describe cumulative processing progress, installation, and a qualification expectation. They do not establish universal High-NA deployment, exact adoption timing for every foundry, system purchase prices, per-chip cost savings, or yield gains. ASML supplies the platform specifications and several expected-benefit comparisons; imec provides process and ecosystem context while also operating a research facility in collaboration with ASML.
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