The Tool Desk
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Where AI fits in chip development
Chip development involves choices and checks across multiple stages. AI can assist with particular tasks in those stages; it is not a single replacement for the engineering process. Performance, power, and area—often shortened to PPA—are common objectives when comparing designs.
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Exploring design options and optimizing PPA
Bayesian optimization, reinforcement learning, and other AI methods can search large or difficult design spaces and help engineers compare implementation choices. NVIDIA Research describes work spanning RTL, verification, synthesis, physical design, sign-off, and design-for-manufacturing. The practical value is in narrowing or improving options for engineers to evaluate, not in treating a generated choice as automatically correct.
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Generative systems can draft or revise RTL and create formal assertion collateral. In an agentic workflow, a system can generate code, run a simulation or tool check, inspect failures, and attempt a revision. That feedback loop is more meaningful than code generation alone, but success on evaluated tasks does not establish correctness for a different, untested production design.
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Helping engineers use EDA tools
Vendor-described copilots can retrieve tool knowledge, help configure scripts, explain workflows, and generate documentation. These uses target time spent navigating complex software and repetitive tasks; they do not themselves establish that a chip’s design is sound.
Coordinating specialized agents
Announced agentic systems coordinate work such as RTL generation, testbench creation, regression orchestration, debugging, or broader EDA workflows. Coordinating steps is distinct from completing verified sign-off: the evidence for an announced capability should not be mistaken for proof that every result is production-ready.
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Accelerating compute-heavy work
NVIDIA describes GPU acceleration for EDA, lithography, and process simulation. This can speed computing used during hardware development, but it is different from an LLM independently designing a chip.
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What reported results do—and do not—show
The reported figures below come from surveys, vendor announcements, and selected case summaries. They describe different tasks and evidence types, so they are not a head-to-head comparison or a forecast of what another chip team will achieve.
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| Source and date | Reported result | Scope and qualification |
|---|---|---|
| Capgemini Research Institute, 2024 | 50% said their organization was investing in generative AI to shorten design cycles. | Survey of 167 respondents from integrated device manufacturers (IDMs), fabless design firms, and EDA firms. This measures reported investment, not proven cycle-time reduction. |
| Deloitte, 2024: Cadence case | 14% improved performance and 3% lower power. | Reported example of AI use on a 5 nm mobile chip with one engineer for 10 days, compared with 10 engineers for several months. It is a case report, not a general expected outcome. |
| Deloitte, 2024: NVIDIA case | 25% smaller circuits at similar performance. | A reported reinforcement-learning example. The result should be read as specific to that case, not as a result for every circuit or design flow. |
| Synopsys, 2025 announcement | 30% faster ramp time for early-career engineers; 2× average improvement in script time-to-solution; 10–20× faster PrimeTime script generation. | Synopsys-reported customer or application outcomes for the named uses, not independent comparative findings. The announcement’s individual outcome conditions are not stated here. |
| NVIDIA, 2026 | 97.1% average pass rate across nine evaluated task categories. | NVIDIA-reported result for Nemotron 3 Ultra in the ACE-RTL agent loop on the stated benchmark categories. A benchmark pass rate does not establish production-chip correctness or independent verification. |
These figures are useful as examples of where teams and vendors report value, but the available material does not establish a neutral, independent production-scale productivity figure. In particular, a task benchmark, a selected project, and a survey answer measure different things.
Why verification remains central
AI can generate plausible RTL or suggestions that still contain errors. Simulation and tool feedback can help identify failures and guide revisions, but the reviewed evidence does not support the claim that AI removes emulation, experiments, design review, or final verification. As NVIDIA chief scientist Bill Dally put it, “We would like to collapse that space, what the really long pole is design verification,” referring to efforts to prove designs more quickly.
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One reported example of AI use across development is OpenAI’s Jalapeño ASIC project, where AI was used for design work and kernel writing and optimization while engineers guided the systems. OpenAI hardware lead Chris Ho described the possible baseline as “a very talented team with the help of AI.” That is an account of one project, not evidence that other teams can reproduce its schedule.
How to evaluate an AI chip-design tool
Compare tools by the work they actually support and the evidence behind their claimed benefits. Useful questions include:
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- Which stage is covered? Check whether the tool supports RTL, verification, optimization, physical design, simulation, lithography, or another specific task.
- Does it suggest or execute? Distinguish a system that drafts content from one that coordinates tool runs and revisions. Neither distinction alone proves the result is correct.
- What checks are built into the workflow? Find out how simulation, formal checks, regression runs, and human review fit into generation and revision.
- How is design data handled? Ask what proprietary design information is processed and what deployment or data controls are available.
- What supports the claimed result? Identify whether a figure comes from a benchmark, a vendor announcement, a customer-specific case, or a survey—and whether the task and conditions resemble your own work.
The available sources do not provide a neutral, apples-to-apples ranking of commercial platforms. A useful comparison therefore starts with the engineering task, validation path, data requirements, and evidence for the specific outcome a team wants to improve.
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