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High-NA EUV keeps the same 13.5 nm light as conventional EUV but uses projection optics with a higher numerical aperture: 0.55 instead of 0.33. That change can resolve finer patterns and may let chipmakers print selected layers in fewer exposures. It also narrows the focus window and raises equipment and process-control demands. As of September 2026, High-NA has reached selective production use, but it is not a universal replacement for conventional EUV.
What changes when EUV becomes High-NA?
The key difference is the scanner’s optics, not its light source. Both conventional EUV and High-NA EUV use light with a 13.5 nm wavelength. Conventional ASML NXE systems have a numerical aperture (NA) of 0.33; ASML’s EXE High-NA systems raise it to 0.55. NA describes the optical system’s ability to collect and focus light. A higher NA can project a finer image onto the wafer.
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That is why “High-NA” is not another name for a smaller process node. It describes a lithography system. A chip’s node label, such as “2 nm,” is not a direct measurement of every transistor feature, and a scanner’s quoted resolution or critical dimension does not determine a chip’s node name.
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|---|---|---|
| ASML platform | NXE | EXE |
| Numerical aperture | 0.33 | 0.55 |
| Exposure wavelength | 13.5 nm | 13.5 nm |
| Resolution implication | Can print very small patterns; some layers may require multiple patterning steps. | Can resolve finer images; ASML describes an 8 nm critical dimension for EXE. |
| Focus window | Less constrained than at 0.55 NA, all else being equal. | Reduced depth of focus makes focus control and process integration more demanding. |
| Potential patterning effect | Some tight patterns may need multiple exposures and associated process steps. | May print some such patterns in one exposure, potentially reducing patterning steps on selected layers. |
The table describes platform-level differences, not a guarantee for every design or wafer layer. ASML’s 2024 explainer summarizes the aperture change: “And it’s called High NA EUV because we’ve increased the NA from 0.33 in our NXE systems to 0.55 in EXE systems.”
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Why higher NA can print finer features—and why it is not a free resolution upgrade
More optical resolving power
In lithography, the projection optics form an image of the mask pattern on a photosensitive resist coating the wafer. Increasing NA improves the optics’ ability to resolve closely spaced details. The wavelength has not changed; the optical system is gathering and focusing light differently. ASML gives an 8 nm critical dimension for EXE, but that figure should be understood as a system capability, not a promise that every printed feature on a production chip will measure 8 nm.
Another useful distinction is between a feature’s critical dimension and its pitch. Critical dimension describes a width or other key dimension in a pattern; pitch refers to the repeat distance between corresponding features. Imec’s 2024 demonstration reported 16 nm-pitch line-and-space images. That pitch is not a claim that the lines themselves are 16 nm wide, nor is it a transistor dimension or a process-node designation. These measurements describe different aspects of a pattern and should not be treated as interchangeable.
A narrower depth of focus
The trade-off is depth of focus: the range of wafer positions over which the projected image stays acceptably sharp. Imec explains that higher NA reduces this range. A wafer is not a perfectly flat target, and small variations in its surface, resist coating, focus setting, or integrated process can affect whether a fine image prints reliably. As a result, achieving the theoretical resolution depends on controlling the actual process window, not only on the scanner’s optical specification.
Resolution, yield, and production cost are different questions. A finer image does not by itself establish that a process will yield more good chips, run faster, or cost less. Those outcomes depend on how the scanner performs with the chosen layer design and the rest of the manufacturing process.
This tighter focus budget is one reason nominal resolution is only a starting point for process evaluation. A manufacturer must determine whether the patterned image remains acceptable over the range of wafer conditions encountered in an actual flow. The relevant combination includes wafer topography, resist behavior, focus control, and process integration. Imec identifies those as material considerations for High-NA, but the cited descriptions do not supply a single numerical focus tolerance or universal production recipe applicable to every layer.
A redesigned platform, not a simple adjustment
Moving to 0.55 NA required a new optical design. Imec describes the High-NA mirrors as twice as large and ten times heavier than those in the preceding generation, and notes the use of anamorphic optics. These changes help explain why High-NA involves a new scanner platform and a broader engineering effort rather than a dial turned on an existing 0.33-NA machine.
The new design also means that introducing High-NA is a platform transition, not merely swapping one optical component in an otherwise unchanged production line. Scanner development, facility and research infrastructure, tool certification, and process work all contribute to readiness. The mirror-size and weight comparisons illustrate the scale of the optical redesign; they are not, on their own, measures of productivity, cost, or fab-floor footprint.
How High-NA may change patterning on a chip
A chip is built through many process steps, and lithography patterns different layers in that stack. When one exposure cannot create the required pattern at the needed resolution, a manufacturer may use multiple patterning steps. In broad terms, those steps divide a difficult pattern across exposures and process operations. High-NA’s finer imaging capability may allow some patterns to be printed with one exposure where a 0.33-NA process would use double or triple patterning.
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The possible benefit is selective: fewer exposures can simplify the sequence for a particular layer, reduce cycle complexity, and potentially avoid some associated masks or process operations. It does not follow that an entire chip needs fewer exposures, or that every layer is cheaper. The actual comparison depends on the layer’s design, exposure count, throughput, yield, masks, and integration with the surrounding process. ASML’s 2024 annual report presented reduced double or triple patterning as a potential benefit, not a universal result.
That distinction matters because chip manufacturing is a stack of many patterned layers, each with its own geometry and integration needs. A High-NA exposure may be useful where a particular pattern is difficult for a 0.33-NA flow, while another layer may not need the extra resolution. Even if High-NA replaces multiple patterning on one layer, the overall flow still includes the other lithography and process steps needed to build the device. A layer-by-layer decision is therefore more informative than asking whether a whole chip is simply “made with High-NA.”
What a research demonstration establishes
In 2024, imec reported single-print images of 16 nm-pitch line-and-space patterns made with an ASML TWINSCAN EXE:5000 in its joint High-NA lab. This is evidence that the system demonstrated that patterning capability in a research setting. It is not a production-yield result or a statistic about a commercial chip. A lab image shows what can be patterned under the reported demonstration conditions; manufacturing readiness also requires process integration, repeatability, throughput, and acceptable yield.
It is useful to distinguish three stages when reading claims about a new lithography platform. A laboratory demonstration shows a pattern was printed under specified experimental conditions. Tool certification and research and development involve further qualification and process work. Volume production is a separate claim about the use of the technology in manufacturing, and even then, a report about selected layers or a subset of products should be kept within that stated scope. These categories are not interchangeable milestones.
What it takes to manufacture with High-NA
The resolution gain shifts pressure onto the rest of the process. Imec identifies wafer topography, resist, focus control, and process integration as important considerations because the depth of focus is smaller. These factors interact: the useful question is not just whether a scanner can resolve a pattern, but whether the pattern can be printed consistently across the wafer and integrated into a working production flow.
- Wafer and focus control: A narrower focus window increases the importance of managing surface variation and accurately setting focus.
- Resist and pattern formation: The resist process must support the desired image and fit the tighter imaging conditions.
- Overlay and integration: A new layer has to align with existing patterns and work with the rest of the process. Imec’s March 2026 description of its EXE:5200 highlighted overlay performance and process stability as system attributes, but that characterization is imec’s, not a universal measured result across production layers.
- Factory and ecosystem readiness: The scanner is one part of a manufacturing system. Research facilities, customer qualification, and process-development work are part of bringing a new exposure platform into use.
Overlay is the alignment of a newly patterned layer with features already created on the wafer. It matters because advanced chips depend on many layers being placed in the intended relationship. A system-level statement about improved overlay is relevant to that challenge, but it should not be read as proof that every High-NA layer achieves a given alignment result in every production environment.
Imec CEO Luc Van den hove described the EXE:5200 in a March 2026 imec announcement as offering “unmatched resolution, improved overlay performance, high throughput, and a new wafer stocker that improves process stability and throughput.” This is imec’s characterization of the system, not an independently established comparison across all manufacturing layers. The mention of a wafer stocker also illustrates that readiness involves handling and process stability around the exposure tool, not only the optics that form the image.
Imec announced the arrival of an ASML EXE:5200 at its research facility on March 18, 2026. That milestone illustrates the role of research infrastructure in developing processes alongside deployment at chipmakers’ facilities; the arrival itself is not evidence that the platform is already in broad commercial use.
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How much is High-NA being used?
High-NA has moved beyond laboratory demonstrations, but the strongest recent production evidence is specific in scope. On September 7, 2026, Intel Foundry and ASML reported that Intel had processed more than one million wafers across tool certification, research and development, and volume production on select layers for a subset of Core Ultra Series 3 (Panther Lake) processors. The total includes activity beyond volume production; it does not mean that one million commercial chips were made with High-NA, nor that all layers in those processors used it.
Intel also reported that selected layers of its 18A process patterned with High-NA delivered performance meeting or exceeding comparable layers patterned with NXE tools. This is a company-reported result for selected layers. It should not be generalized to every layer, manufacturer, process, or measure of performance.
The wording of the wafer milestone matters: it combines wafers processed during several kinds of activity, including certification and R&D, with select-layer volume production. It is not a count of wafers all processed in volume production, and the reported figure does not establish that High-NA was used for every layer on each wafer. Nor should the result be recast as a count of finished processors. The announcement is evidence of selective manufacturing use, not universal deployment.
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A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11Earlier expectations should be read as dated forecasts, not as current deployment facts. ASML’s 2024 materials anticipated research and development beginning in 2024–2025 and high-volume manufacturing around 2025–2026. Its 2025 annual report later described maturing the platform toward high-volume manufacturing requirements by the end of 2026, with customer insertion in 2027–2028. The September 2026 Intel and ASML announcement provides a later, more specific report of select-layer volume production. Together, these milestones describe a gradual and selective introduction, not a single industry-wide switchover date.
The timeline is best read as a sequence of expectations and reported milestones. An anticipated date for high-volume manufacturing is not itself proof that all manufacturers have reached that stage. Conversely, a company’s report of selected-layer production does not imply that the broader industry has adopted the system. The announcements describe different scopes: platform maturation, expected customer insertion, and a specific customer’s reported activity.
Is High-NA EUV cheaper or faster?
There is no universal cost-per-layer comparison established by the cited primary-source claims. High-NA may reduce the number of patterning steps on a layer, but that possible saving must be weighed against the layer’s exposure plan, scanner throughput, masks, yield, and process integration. A scanner that enables a simpler patterning sequence does not automatically make the whole layer or chip less expensive.
Nor do the cited claims establish a general throughput advantage or yield advantage across production layers. Imec’s March 2026 statement about the EXE:5200 described high throughput and improved overlay performance as benefits, while its report on the 16 nm-pitch images documented a research demonstration. Those are distinct kinds of evidence: a system characterization and a lab result are not broad, independent production comparisons.
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There is also no single break-even point that can be inferred from the aperture numbers alone. The comparison has to account for both sides of the flow: the potential reduction in multiple-patterning work and the full requirements of using the new platform. Exposure count, mask use, throughput, yield, and integration are all part of the layer economics. Those values can differ by design and process, so a result for one layer would not automatically settle the economics for another.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to interpret the EUV-versus-High-NA comparison
For chip buyers, the distinction is not a simple ranking in which newer optics automatically make every chip better. For process engineers and manufacturers, the decision is whether the finer imaging capability solves a real patterning constraint on a given layer while keeping focus, integration, and production performance within acceptable limits.
- Identify the layer and pattern requirement. Ask whether the pattern can be made with conventional EUV in the current flow, or whether it drives additional patterning steps.
- Compare complete exposure flows. Determine whether High-NA can reduce exposures for that specific pattern, rather than assuming it reduces patterning across the whole chip.
- Check the process window. Evaluate focus tolerance, wafer topography, resist behavior, overlay, and integration alongside nominal resolution.
- Separate demonstration from production evidence. A research image establishes a demonstrated pattern; qualification and selective production provide different evidence; broad deployment requires evidence beyond a single layer or customer report.
- Assess the economics using measured layer data. Compare exposures, masks, throughput, yield, and integration costs for the actual process. The optical aperture alone cannot answer which flow is cheaper.
This framework also helps avoid common category errors: a 16 nm pitch is not a 16 nm transistor, an 8 nm critical dimension is not a process-node label, and a milestone involving more than one million wafers across several activities is not a count of High-NA-made chips.
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1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsFor readers comparing company announcements, four questions help keep the evidence in proportion: Which scanner platform is being discussed? Does the result concern a laboratory pattern, tool certification, development, or manufacturing? Is the claim about one or more selected layers, or about a broader product flow? And does the statement report a measured result, a company characterization, or a future expectation? Applying those distinctions prevents technical capability, deployment status, and economic benefit from being collapsed into one claim.
What High-NA means for the future of chipmaking
High-NA extends EUV lithography by improving the projection optics while retaining the established 13.5 nm wavelength. Its main manufacturing promise is more resolution and, on selected layers, the possibility of fewer patterning steps. Its central challenge is translating that capability into a stable, integrated process despite a narrower focus window and new equipment demands.
The evidence through September 2026 supports selective use and continued process development, not universal replacement of 0.33-NA EUV. Whether High-NA becomes the better choice depends on the demands and economics of individual layers, as well as manufacturers’ readiness to integrate the platform.
In practical terms, conventional EUV and High-NA EUV are complementary options rather than an old-versus-new choice for every layer. The 0.55-NA system expands the resolution available to chipmakers, while the 0.33-NA generation remains part of the comparison for layers that do not require the additional imaging capability. The manufacturing question is where that added capability solves a specific patterning problem enough to justify the full process change.
Frequently Asked Questions
What is the main difference between EUV and High-NA EUV?
Both use 13.5 nm light. Conventional ASML NXE scanners have a 0.33 numerical aperture, while EXE High-NA scanners raise it to 0.55. The higher NA can resolve finer images, but it also reduces depth of focus and makes process control more demanding.
Does High-NA EUV use a shorter wavelength?
No. High-NA EUV retains the 13.5 nm wavelength used by conventional EUV. The change is in the projection optics and their numerical aperture, not the light source wavelength.
Does High-NA mean a 2 nm chip or an 8 nm transistor?
No. High-NA describes the scanner’s optical system, not a process-node label. ASML cites an 8 nm critical dimension for EXE as a system capability; it is not a promise that every feature on a production chip measures 8 nm. A node name such as “2 nm” is not a direct measurement of every transistor feature.
Can High-NA EUV reduce the number of exposures?
It may allow some patterns to be printed in one exposure where a 0.33-NA flow would use double or triple patterning. The benefit depends on the particular layer and its design; it does not mean every chip or every layer needs fewer exposures.
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Is High-NA EUV cheaper or faster than conventional EUV?
There is no universal cost-per-layer, yield, or throughput advantage established across production layers. A comparison needs layer-specific information about exposures, masks, throughput, yield, and process integration. Potentially fewer patterning steps do not by themselves prove a lower total cost.
What did imec’s 16 nm-pitch demonstration show?
In 2024, imec reported single-print images of 16 nm-pitch line-and-space patterns using an ASML TWINSCAN EXE:5000 in its joint High-NA lab. It was a research demonstration, not a production-yield result or a claim about a commercial chip.
What does Intel’s one-million-wafer High-NA milestone mean?
In September 2026, Intel Foundry and ASML reported more than one million wafers processed across tool certification, R&D, and volume production on select layers for a subset of Core Ultra Series 3 (Panther Lake) processors. The total includes activity beyond volume production; it is not a count of one million commercial chips made with High-NA.
The Bottom Line
Bottom line: High-NA EUV keeps the 13.5 nm wavelength but raises numerical aperture from 0.33 to 0.55, improving potential resolution while tightening the focus window. It may simplify patterning on selected layers, but it is not automatically cheaper, faster, or a replacement for conventional EUV everywhere. The right comparison is layer-specific and weighs resolution, process control, integration, throughput, yield, and total patterning steps.
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