Embedded passives can improve power integrity in AI systems, but they cannot fix the power-delivery problem on their own. By placing capacitance closer to an accelerator, package-embedded capacitors can reduce parasitic effects and help limit voltage droop during fast load changes. Their value depends on the rest of the power-delivery network (PDN), including converter placement, interconnects, board-level decoupling, thermal conditions and reliability.
Why AI accelerators stress the power-delivery network
A PDN carries power from conversion and distribution circuitry to the active load. When an accelerator’s current demand changes quickly, resistance and inductance along that path contribute to a deviation in supply voltage. Designers therefore care about PDN impedance across relevant frequencies, as well as transient droop during load changes.
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Decoupling capacitors provide local charge storage. But distance and parasitic inductance limit how effectively a capacitor can respond to fast changes. Putting capacitance inside a package or substrate can shorten part of the electrical path to the load and reduce parasitic effects. The IEEE Electronics Packaging Society’s Heterogeneous Integration Roadmap states that “Package-embedded capacitors have lower parasitics and improve the electrical performance at higher clock speeds (>350 MHz).” That statement describes the roadmap’s context; it is not a guarantee for every package or system.
What embedded capacitors have demonstrated
Package-substrate integration
A 2024 IEEE ECTC paper on an integrated Package Solution (iPaS) substrate reported an impedance of 1 mΩ at 1 MHz. In the paper’s comparison, the module reduced the number of surface-mount capacitors by more than 60% while achieving almost the same voltage droop as a general module. When the surface-mount capacitor count was not reduced, the reported droop improved by 14 mV, or 10%. These are results for that module and its comparison, not universal performance figures. IEEE ECTC 2024 paper.
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Capacitance density figures
The roadmap describes package-embedded decoupling densities of 2 µF/mm² with approximately 100-micron films, and a density of 20 µF/mm³ for the technology it discusses. Those figures are not generic specifications for all embedded capacitors; actual density and performance depend on the material and integration approach. IEEE Heterogeneous Integration Roadmap.
Deep-trench capacitors in a silicon interposer
A 2020 study of a CoWoS logic-HBM2E design reported a deep-trench capacitor integrated into the silicon interposer with a capacitance density of 300 nF/mm². In that studied design, the capacitor was associated with lower impedance and first voltage droop in the logic-core area, and lower impedance and simultaneous-switching noise in the HBM2E PHY area, compared with the design without the deep-trench capacitor. This evidence applies to that platform and comparison. IEEE ECTC 2020 paper.
Why capacitance alone is not a system-level fix
Embedded capacitors address local charge storage and part of the path between stored charge and the load. They do not replace the power converter or eliminate losses and impedance elsewhere in the network. A design still has to manage conversion, routing, package and board interconnects, and decoupling at multiple points.
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Vertical power delivery tackles a related but different part of the problem by changing how power reaches the load and shortening high-current paths. An IEEE APEC 2024 paper describes a vertical solution for machine-learning ASICs capable of supplying more than 1,000 A at 0.8 V. At a 1,000 A load, it reports 70% lower I²R loss than the conventional lateral design it studied. Those figures belong to the paper’s architecture and comparison; they do not establish a universal benefit for vertical power delivery. IEEE APEC 2024 paper.
On-chip decoupling optimization and package placement are also studied as ways to control cascaded PDN impedance. Embedded capacitance, converter location, vertical delivery and board-level components are complementary design choices, not interchangeable solutions. IEEE ECTC 2024 paper.
How to evaluate an implementation
A meaningful comparison should use the target accelerator, package and operating conditions rather than a single headline capacitance or droop number. Evaluate candidate designs against:
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- PDN impedance: Measure across the frequency range relevant to the load and its switching behavior.
- Transient response: Compare voltage droop and recovery under comparable load-step conditions.
- Path parasitics: Account for interconnect resistance, inductance and distance from the capacitor or converter to the load.
- Integration trade-offs: Consider surface-mount capacitor count, package area and achievable integration density.
- Power conversion and routing: Assess converter efficiency and routing loss as well as local decoupling.
- Operating life: Include temperature, aging and reliability qualification.
- Manufacturing constraints: Check package integration requirements and production feasibility for the specific design.
A 2024 open-access study of a realistic high-current server system identifies temperature and decoupling-capacitor aging as factors that can affect PDN performance. It does not establish that embedded capacitors are categorically more or less reliable than surface-mounted alternatives. Reliability must be qualified for the chosen implementation and operating conditions. Journal of Power Electronics, 10 September 2024.
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Multilayer ceramic capacitors (MLCCs) are a board-level decoupling option, not a substitute for custom package-embedded capacitance, deep-trench capacitors or power modules. The IEEE roadmap includes MLCCs among the technologies used in lower-voltage power-delivery networks, including 0.8–12 V. Their role depends on where they sit in the PDN and the needs of the particular design. IEEE Heterogeneous Integration Roadmap.
Embedded and board-level approaches can coexist: the design question is how each contributes to impedance and transient performance at its location, not which one universally replaces the others.
What the evidence does—and does not—show
The cited papers demonstrate improvements or useful design characteristics in particular modules, packages and architectures. They do not establish a universal ranking of embedded capacitors, MLCCs or power-delivery topologies, nor do they provide a reliable market-wide statistic for adoption, cost, production yield or total-system savings. An engineering decision should be based on measurements and qualification for the specific accelerator and package rather than extrapolating an individual paper’s result to all deployed AI systems.
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