Arm Scalable Matrix Extension (SME) is an extension to the Arm processor architecture and programming model for matrix operations. It builds on SVE and SVE2, adding a two-dimensional matrix storage state called ZA, instructions that accumulate vector outer products into ZA, and a Streaming SVE mode.
What SME adds to the Arm architecture
SME is not a separate accelerator or chip. It adds architectural state, instructions and an operating mode that software can use when the processor implements the extension. Arm describes SME as building on SVE and SVE2 to improve support for processing matrices.
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The central addition is ZA, a two-dimensional architectural storage array for matrix tiles. Software and SME instructions can work with ZA as vectors, tiles or tile slices, and can move data between ZA, vector registers and memory.
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SME’s outer-product instructions take two vector inputs and accumulate, or subtract, their outer product into a ZA tile. Repeating those operations lets software build a matrix multiplication: successive input columns and rows contribute to the output tile. The ZA tile holds the accumulating matrix data while the computation proceeds.
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This describes the architectural mechanism, not a guaranteed speedup. Actual performance depends on the processor, software, data types and workload; Arm’s architectural overview does not establish a universal performance figure.
What Streaming SVE mode means
SME provides a streaming mode in which SME operations and a subset of SVE2 instructions are available. Streaming mode is distinct from ordinary SVE operation, and not every SVE2 instruction is available in it. Arm also distinguishes the streaming vector length (SVL) from the non-streaming vector length (NSVL); they can differ.
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Vector lengths and ZA capacity depend on implementation
The vector length is implementation-dependent. Arm’s 2024 introduction lists streaming vector lengths of 128, 256, 512, 1,024 and 2,048 bits; that list describes architectural possibilities, not a promise that every processor supports every length. In one illustrative 256-bit SVL example, ZA is 32 × 32 bytes, or 1,024 bytes. This is an example configuration, not a universal ZA size.
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Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteFor a specific processor, check its official product or silicon documentation for SME support and implemented vector lengths. The architecture name alone does not establish that a given processor implements SME.
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SME compared with SVE, NEON and SME2
| Architecture feature | What distinguishes it |
|---|---|
| NEON | Uses fixed-width vector processing. |
| SVE and SVE2 | Use scalable vectors; they are the foundation on which SME builds. |
| SME | Adds ZA matrix-tile state, vector outer-product operations and Streaming SVE mode. |
| SME2 | Extends SME with multi-vector data processing, multi-vector load/store and multi-vector predication. |
Arm’s 2024 overview also describes later extensions building on SME2, including 2:4 structured sparsity and quarter-tile operations. Those are later additions, not part of the base SME definition.
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What SME means for software and hardware
- Software can use SME’s matrix-oriented state and instructions when they are supported by the target processor and software environment.
- Streaming SVE mode has its own vector length and instruction availability; code should not assume it behaves exactly like ordinary SVE operation.
- Support and implemented capabilities are processor-specific. Confirm them in model-specific documentation rather than assuming all Arm processors include SME.
- SME describes an architectural capability, not a standalone matrix accelerator or a performance result.
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