The Tool Desk
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A similar node name does not make layouts, hard macros or electrical behavior portable. A port is ready only when target-process signoff is complete and the foundry can accept the data under current tapeout, qualification and supply conditions.
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Start with the product requirements, not the node label
Create a written requirements baseline before comparing processes. Include every condition that can force a process choice:
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- Voltage domains, I/O voltages and power-sequencing requirements.
- Clock frequency, throughput, latency, active power, standby power and leakage limits.
- Analog and RF performance, including noise, matching, linearity, frequency range and passive-device needs.
- Memory types and sizes: SRAM, ROM, embedded nonvolatile memory and any compiler options.
- I/O standards, high-speed interfaces, SerDes or PHY requirements, ESD targets and package connections.
- Metal-stack, thick-metal, top-metal, capacitor, resistor, inductor and interconnect requirements.
- Automotive, industrial, medical, aerospace or consumer reliability class, operating temperature and expected product life.
- Expected volume, wafer size, package, test coverage and supply-life expectations.
Compare those requirements with the target process options rather than with its marketing node name. Process portfolios can differ substantially in high-voltage devices, low-leakage choices, embedded memory, mixed-signal support and reliability offerings even when nominal geometries appear similar.
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Obtain and control the target PDK
The process design kit is the controlled definition of how the target technology is designed and signed off. Obtain the current release through the foundry’s access process, read its release notes, and record the exact version used by every design team and vendor.
Check what the PDK actually contains
- Transistor, passive and I/O device models for all required voltage and temperature ranges.
- Standard-cell, I/O, memory and specialty libraries, with characterized timing, power and variation data.
- Layer maps, design-rule manuals, extraction decks, parasitic models and reliability guidance.
- DRC, LVS, design-for-manufacturing, antenna, density, fill, electromigration, latch-up and ESD checks.
- Supported EDA tools, qualified versions, scripts, reference flows and known limitations.
- Model, rule and library change history, including fixes that can invalidate previous results.
GlobalFoundries describes PDKs as supplying models, rules and libraries to EDA tools and identifies DRC, LVS and ESD compliance as part of enablement. That does not mean every PDK has the same checks or maturity. Ask the target foundry which checks are mandatory for tapeout, which are advisory, and how waivers are reviewed.
Build a rule and layout delta list
Do not begin by copying the source layout. First map the differences between source and target processes:
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- Minimum geometry, enclosure, overlap, via, cut-mask and multi-patterning requirements.
- Metal width, spacing, density, fill, slotting, current-density and electromigration limits.
- Antenna rules, latch-up structures, well and substrate ties, guard rings and isolation requirements.
- ESD devices, pad-ring rules, seal-ring requirements and reliability structures.
- Special options such as thick top metal, high-voltage devices, capacitors, inductors or RF layers.
Classify every rule as a hard signoff requirement, a recommended design practice or a condition requiring a formal waiver. The GF180MCU documentation, for example, distinguishes mandatory process-specific DRC rules from design guidance and requires violations to be waived before tapeout acceptance. Its exact limits belong to that process and must not be generalized to another technology.
A source-process-clean database proves only source-process compliance. It says nothing about target-process DRC, LVS, extraction, antenna, density or reliability status.
Inventory every IP block and hard macro
Make a block-by-block inventory before estimating schedule. Include SRAM and ROM compilers, PLLs, SerDes, PHYs, I/O cells, analog and RF blocks, embedded memories, security modules and third-party hardened IP.
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Questions for each block
- Is an exact target-process implementation available, including the required voltage, speed, temperature and package options?
- What characterization corners, silicon results and production history support it?
- Which EDA versions, wrapper cells, power intent and physical abstracts does it require?
- Can the license be transferred, modified or sublicensed for the new foundry?
- Who owns integration, recharacterization, failure analysis and long-term support?
TSMC describes process-specific IP lifecycle assessments that include pre-silicon review and test-chip assessment for hardened IP. It also explicitly cautions that silicon-verified IP is not guaranteed to work in every design environment or achieve a particular production yield. Treat an IP listing as an opportunity for due diligence, not as proof that the block will drop into your design.
TSMC reported a catalog of more than 60,000 IPs in August 2023, spanning dozens of IP types and hundreds of its process technologies. That dated ecosystem figure is not a current availability count and does not establish support for any particular macro or process.
Verify EDA tools and the migration flow
Ask the foundry and each EDA supplier for a certified tool-and-version matrix. Confirm support for synthesis, static timing, simulation, power analysis, place-and-route, custom layout, extraction, physical verification, reliability analysis and signoff reporting.
Require a reproducible reference flow
- Set up the target PDK, technology files, libraries and version-controlled scripts in a clean environment.
- Run synthesis and timing with target standard-cell libraries, operating corners and variation models.
- Run place-and-route with target routing layers, via rules, congestion limits, antenna handling and density requirements.
- Run circuit simulation, extraction and power analysis using target devices, parasitics and temperature corners.
- Run DRC, LVS, antenna, density, extraction and electrical or reliability decks supplied for the target release.
- Record tool versions, deck hashes, waivers, run options and reports so the result can be reproduced at tapeout.
TSMC’s EDA Alliance material describes flows spanning design, simulation, implementation, verification and extraction, and lists analog and RF migration reference flows for specific technology transitions. Such a reference flow is evidence of enablement for that transition; it is not a universal promise that another foundry pair will support database translation.
Re-evaluate analog, RF and custom layout behavior
Digital synthesis can hide many process changes, but analog, RF and custom blocks expose them immediately. Device dimensions, model equations, passive structures, matching rules, well options, substrate behavior and parasitics can all change.
Determine whether the migration requires schematic conversion, transistor resizing, bias redesign, passive replacement, common-centroid changes, guard-ring updates, layout redraw, extraction recalibration or circuit optimization. Simulate noise, offset, gain, phase noise, linearity, matching, startup and stability across target corners. A layout database that imports successfully can still fail electrically or violate target spacing and density rules.
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Measure PPA with target data
Re-run the complete design with target-process models, libraries, parasitics and operating corners. Compare:
- Timing and frequency at every required voltage, temperature and process corner.
- Dynamic, leakage and standby power, including power-up and retention behavior.
- Die area, utilization, congestion, routing overflow and memory or macro footprint.
- Noise, matching, linearity, jitter, phase noise and analog margins where applicable.
- IR drop, electromigration, thermal limits, ESD margins and other reliability measures.
Do not import performance claims from a different design. TSMC says its N6 process retains backward-compatible design rules, models, IP, design flow and EDA availability with N7. That is an example of compatibility deliberately engineered within one N7/N6 platform, not a general rule for unrelated foundries or process pairs.
Plan target-process verification and tapeout acceptance
Define signoff ownership and acceptance criteria before layout freeze. The target flow should cover:
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- Foundry-qualified DRC and LVS with the exact PDK release.
- Parasitic extraction and post-layout simulation for digital, analog and RF blocks.
- Antenna, density, fill, latch-up, ESD, electromigration, IR-drop and thermal checks as applicable.
- Memory, I/O, pad-ring, seal-ring, mask-option and reticle data checks.
- Waiver format, approval authority, expiration and audit trail.
- Required stream-out format, layer map, naming convention, documentation and tapeout package.
Ask the foundry to confirm which violations block acceptance. GlobalFoundries’ published wording is unambiguous: “Prior to design data submission using GlobalFoundries Foundry Service Request Specification (CX-008) procedure, the design must pass all DRC tests.” Your target process may use a different submission specification, but the principle is the same: a clean source signoff is irrelevant unless the target signoff is complete.
Assess qualification, reliability and manufacturing readiness
A technically functional test chip is not the same as a production-ready process. Request evidence relevant to your product and market:
- Process qualification status, reliability reports and characterization plans.
- Operating-life, temperature-cycle, humidity, voltage-stress and other applicable reliability results.
- Wafer acceptance criteria, inline monitoring, defect control and failure-analysis capability.
- Package assembly, test-program and burn-in compatibility with the target device.
- Yield-learning data, test-chip results and a defined mechanism for sharing yield information.
- Fab location, capacity, expansion plans, second-source strategy and product-lifecycle commitments.
TSMC describes technology qualification before transfer to fabs, quality and reliability controls from development through mass production, and release criteria. Those descriptions do not establish the qualification status, expected yield, lead time or capacity for your specific process, product or customer. Obtain current, process-specific evidence under appropriate confidentiality terms.
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Estimate schedule, cost and ownership from the real scope
Build the estimate from work packages rather than from a generic “porting” multiplier:
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- IP replacement, re-licensing, recharacterization or redesign.
- EDA enablement, scripts, flow conversion and regression infrastructure.
- Digital re-synthesis, physical implementation and custom-layout migration.
- Verification closure, extraction, reliability analysis and waiver management.
- Test-chip or multi-project-wafer work, if needed to retire process or IP risk.
- Masks, tapeout slots, prototype wafers, package, test, sample validation and product qualification.
- Ramp support, failure analysis, yield learning and sustaining engineering.
Assign a named owner for each task and clarify who may modify third-party IP, who pays for rework and who owns resulting layout or models. There is no defensible universal port cost, duration, yield improvement or redesign rate; all depend on process, design complexity, IP, validation depth and available capacity. Get commercial quotes and supply commitments directly from the foundry and suppliers.
Use one scorecard for every candidate process
Compare alternatives with the same evidence requests instead of scoring public marketing claims. A practical scorecard is:
| Evaluation area | Evidence to request |
|---|---|
| Electrical and process fit | Supported devices, voltage options, memory, analog/RF features, metal stack and reliability class mapped to product requirements. |
| PDK maturity | Controlled release, models, libraries, rules, extraction data, signoff decks, release notes and qualified tool versions. |
| IP and macros | Target-process availability, characterization, silicon or production evidence, licensing terms and support ownership. |
| EDA and migration flow | Certified versions, reference scripts, analog/RF migration guidance and reproducible signoff flow. |
| PPA and redesign burden | Target-corner timing, power, area, noise, matching, linearity, margins and identified redesign work. |
| Verification and tapeout | Mandatory checks, waiver process, data formats, mask options and formal acceptance criteria. |
| Qualification and reliability | Process qualification, reliability results, characterization plans, package/test compatibility and failure-analysis support. |
| Schedule, cost and supply | Quotes, tapeout slots, prototype path, capacity, lifecycle, lead time, ownership and supply commitments. |
Require a document, report, demonstration or named commitment for each row. If a candidate cannot provide evidence, record that gap as a project risk rather than silently treating it as equivalent to a qualified option.
Common porting mistakes and their remedies
Assuming the same node means the same rules
Why it fails: Layer stacks, devices, vias, density, antenna and reliability limits are process-specific.
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Remedy: Build the delta list from controlled target documents and rerun all target signoff decks.
Reusing hard IP without target evidence
Why it fails: A macro can depend on undocumented models, parasitics, wrappers, voltage limits or manufacturing assumptions.
Remedy: Obtain an exact target-process version or budget redesign, characterization and validation.
Trusting an imported layout database
Why it fails: Geometrical translation does not preserve electrical behavior, matching, extraction or reliability.
Remedy: Recreate or adapt schematics and layout under target rules, then verify post-layout behavior.
Leaving qualification until after tapeout
Why it fails: Package, test, reliability or supply constraints can invalidate an otherwise clean design.
Remedy: involve manufacturing, package, test and quality teams while selecting the process and before committing masks.
Decision gate before committing to the port
Proceed only when the target process has a documented fit, a controlled and usable PDK, a credible path for every hard macro, certified tools and flows, target-process PPA results, clean verification or approved waivers, and evidence that qualification, package, test and supply plans match the product. If any of those areas remains an assumption, treat the project as risk retirement—often with a test chip or prototype run—rather than as a straightforward layout migration.
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