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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallOn the original ESP32, the “secret processor” is the Ultra Low Power (ULP) coprocessor: a small, specialized controller that can monitor inputs while the main processors are in deep sleep and request a wake-up when a condition is met. It is not a second general-purpose CPU running your application. The original ESP32 uses a timer-driven finite state machine (ULP FSM), with a constrained instruction set and access to selected memory and peripherals.
What the original ESP32 ULP can do
The ULP FSM is intended for limited measurement and monitoring while the main processors are in deep sleep. Espressif documents using it to measure with the ADC and temperature sensor, and to work with external I2C sensors. It can also check GPIO states and decide whether the main system should wake.
Two documented examples show the intended scale of work:
- Count pulses arriving on an input while the main processors sleep.
- Periodically measure an ADC voltage, compare it with a threshold, and wake the system if the reading exceeds that threshold.
These are periodic checks and simple decisions, not continuous full-speed application processing. The main program prepares the ULP task and handles the work that requires the main processors after a wake-up.
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How the ULP FSM runs
The main application loads the ULP program into RTC memory and starts it. A timer driven by the RTC slow clock then starts the FSM at the configured interval. Each run begins at the program entry point and continues until the program halts or encounters an illegal instruction; the FSM then powers down until the timer starts it again.
Espressif’s documentation gives about 133 microseconds as a minimum interval for its stated default 150 kHz configuration, including startup and shutdown overhead. That is a documented implementation detail for that configuration, not a universal timing guarantee or a measure of battery-life improvement.
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Why it is not a second application CPU
The original ESP32 FSM has a deliberately small programming and resource model. Espressif documents four general-purpose 16-bit registers, 32-bit instructions, and access to an 8 KB RTC slow-memory region addressed in 32-bit words. It can also interact with selected registers in RTC control, RTC I/O, and SAR ADC peripherals.
Programs for this FSM use assembly or ESP-IDF macro tooling. Those limits make it suitable for short, focused monitoring tasks, but they do not let it transparently run the main ESP32 application. A task also needs to fit the available instructions, memory, and supported peripheral access.
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ULP hardware differs across ESP32 families
“ESP32” covers multiple chip families, and the ULP implementation is not the same on all of them. Espressif’s current overview distinguishes these types:
| Chip family | ULP type documented by Espressif | Programming-model note |
|---|---|---|
| Original ESP32 | ULP FSM | Assembly or ESP-IDF macros; the constraints described above apply. |
| ESP32-S2 and ESP32-S3 | ULP FSM and ULP RISC-V | Espressif documents the RISC-V model as programmable in C with standard GNU tools. Do not assume that model applies to the original ESP32. |
| ESP32-C5, ESP32-C6, and ESP32-P4 | ULP LP Core | These parts are listed with a different ULP type; the original ESP32 FSM details should not be applied to them. |
Espressif says only one coprocessor type operates at a time on a given chip. The ESP32-S2 and ESP32-S3 can enable both types at compile time and select which to use at runtime. For a project, check the exact chip and the documentation and example for that variant before choosing a ULP program.
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Check sleep and revision settings if wake-up fails
On original ESP32 revision 0 and revision 1 chips, Espressif documents a caveat for the referenced ULP wake-up mode: RTC peripherals must not be forced to remain powered on. The RTC peripheral power domain should be configured as AUTO. If expected wake-ups do not occur, check the chip revision and power-domain configuration along with the ULP program and its timer settings.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What you need to try an example
An ESP32 development board is a practical way to experiment. Espressif’s ESP32-DevKitC V4 documentation describes a board with several module configurations and I/O brought out for peripheral connections. Verify the fitted module: a board described as ESP32-based is not by itself proof that it contains the original ESP32 or supports an example written for its FSM.
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- SupportThree Modes: AP, STA, and AP+STA
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Choose any sensor and wiring to match the particular demonstration. For instance, an ADC threshold example needs a suitable voltage source connected to a supported input; an external I2C example needs a compatible sensor and the correct bus connections. The ULP type, supported peripheral, and chip configuration determine whether a given example applies.
Quick Recap
Espressif documentation
- Ultra Low Power (ULP) coprocessor — ESP32 — ESP-IDF Programming Guide v6.1
- ULP FSM Coprocessor Programming — ESP32 — ESP-IDF Programming Guide v6.1
- Sleep Modes — ESP32 — ESP-IDF Programming Guide
- ESP32 ULP Coprocessor Instruction Set — ESP-IDF Programming Guide
- ESP32-DevKitC V4 — esp-dev-kits documentation
- ULP RISC-V Coprocessor Programming — ESP32-S2 — ESP-IDF Programming Guide v6.1
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