A silicon photonics foundry fabricates photonic integrated circuits (PICs) using a defined manufacturing process. It may also provide the process design kit (PDK), prototype access, and packaging or test services. To choose one, first confirm that its process and PDK support your required devices and how they must be integrated; then compare prototype access, performance evidence, manufacturing readiness, design tools, packaging, test, and written commercial terms.
What is a silicon photonics foundry?
A silicon photonics foundry is a manufacturing provider for PICs: chips that guide, split, filter, modulate, or detect light using fabricated optical components. The foundry’s process defines which components can be made and how they can be combined. The name of a process or wafer size alone does not tell you whether it supports the devices your design needs.
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The foundry relationship can cover more than wafer fabrication. Depending on the provider and platform, it may include design enablement, prototype runs, packaging, assembly, and test. For example, imec describes foundry access through dedicated full-mask runs and, for some technologies, multi-project wafers (MPWs), as well as design and IP services and PIC supply-chain management. GlobalFoundries describes silicon photonics packaging, assembly, and test services.
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What is a photonics PDK, and why does it matter?
A process design kit is the practical interface between a foundry’s manufacturing process and a designer’s electronic design automation (EDA) workflow. It gives the design team process-specific information and resources to create and verify a layout that can be manufactured using that process. GlobalFoundries describes PDKs as process models, rules, and libraries used by EDA tools. AIM Photonics says its PDKs include design guides, design-rule-checking decks, component libraries, and plug-ins or scripts for creating PIC prototypes for its wafer services.
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Before committing to a design, ask for the exact PDK version and review its supported components, models, design rules, EDA compatibility, access conditions, and update policy. A generic EDA tool license does not necessarily include access to a specific foundry’s PDK. Synopsys lists a multi-provider photonic PDK ecosystem and says designers can obtain PDKs from their selected foundry; check both the tool provider’s and foundry’s requirements.
AIM Photonics’ PDK information, GlobalFoundries’ PDK overview, and Synopsys’ photonic PDK page describe their respective design-enablement offerings.
How do you choose a silicon photonics foundry?
Compare candidates against the requirements of the actual PIC and product, not against a process name or a single headline specification. Keep a written comparison, and mark whether each performance figure is measured, demonstrated, qualified, or a roadmap target.
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- Silicon Photonics Design From Devices to Systems
1. Match the device set and integration
List the devices and materials the design requires: for example, passive waveguides and filters, modulators, detectors, silicon nitride (SiN) paths, lasers, or electronic-photonic integration. Check that the current PDK supports the required combination—not just each device in isolation—and ask how any active components are integrated. These options are platform-specific. imec, for example, describes silicon and SiN options and integration routes for III-V lasers, semiconductor optical amplifiers, and lithium niobate modulators; those capabilities should not be assumed to exist in another provider’s process.
2. Check performance at your operating point
Compare process-specific evidence for the wavelengths, modulation format, optical loss, bandwidth, and other conditions that matter to your system. Ask what has been demonstrated on silicon, what is qualified for production, and what remains in development. Vendor figures can help screen candidates, but they are not a neutral, apples-to-apples benchmark across foundries.
For example, GlobalFoundries reports that its silicon photonics generations support up to 100G/λ for Gen 1, are proven up to 200G/λ for Gen 2, and have a stated path to 400G/λ for Gen 3. These are GlobalFoundries’ capability statements, not independently comparable results across providers. GF also reports athermal CWDM filter results of <1 dB insertion loss, <0.2 dB passband ripple, and <−30 dB crosstalk, with performance described as design dependent. Ask what device design and conditions those figures represent before using them in a system budget.
3. Establish how you can make a prototype
Find out whether the candidate offers an MPW run, in which designs share a wafer, or whether your project needs a dedicated full-mask run. An MPW can be a route to prototype access, but availability may be limited to selected technologies. imec documents both full-mask and MPW access for a subset of its iSiPP200 technologies; its public page does not provide a universal schedule or price.
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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsAsk the provider for current submission dates, design constraints, eligibility, mask requirements, fabrication turnaround, and the next opportunity to revise or repeat a design. Confirm these directly for the specific platform and run; do not infer a project schedule from a general service description.
4. Evaluate manufacturing maturity and scale
Compare wafer diameter, the status of the specific process, capacity, process control, and the provider’s scaling plan. A larger wafer does not by itself establish a particular yield, lead time, or allocation for your project.
Platform status claims need a date. Tower Semiconductor’s November 26, 2024 announcement introduced a standard 300 mm silicon photonics offering alongside its 200 mm PH18 platform, which the release described as being in high-volume production at that time. imec describes a mature 200 mm iSiPP200 platform as well as a 300 mm platform. Confirm present status, capacity, and the conditions for a new design with the provider.
5. Include packaging, assembly, and test from the start
Packaging can constrain the PIC layout and determine whether a fabricated chip can connect to the rest of the product. Compare support for fiber attach and optical coupling, electrical interfaces, package design, test access, and the handling of known-good dies. Ask whether the provider supports the exact package and test flow your product needs, rather than assuming that general packaging capability covers it.
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AIM Photonics’ Assembly Design Kit (ADK) supports specified wirebond and fiber-attach configurations and provides templates, verified design data, and multiphysics simulation. Its purpose is to bring supported packaging constraints into the design workflow. GlobalFoundries describes several fiber-attach approaches and packaging, assembly, and test capabilities. The details are provider-specific; confirm the available configuration for your project.
6. Verify tools, models, and support
Check that your team’s EDA environment is supported by the foundry’s PDK and that the kit includes the models, design-rule checks, reference flows, and component information your design process requires. Clarify technical support, licensing, access restrictions, and how PDK changes are communicated. Resolve these points before design work depends on a particular kit or tool flow.
7. Get commercial and qualification terms in writing
Public capability pages generally do not establish the terms of an individual project. Ask each shortlisted provider for written answers on:
- Non-recurring engineering (NRE) and mask charges, wafer pricing, and minimum volumes
- Lead times, available capacity, and any reservation terms
- Yield definitions and the data available for the specific process
- Process-change control, IP protection, data handling, and failure analysis
- Product qualification requirements and the plan for reaching them
Compare like with like: a price or schedule is meaningful only when the run type, design scope, quantities, and service assumptions are clear. Do not treat a public platform description as a quote, a yield guarantee, or a customer-specific commitment.
How do the publicly described foundry options differ?
The examples below are useful for building a shortlist, not ranking suppliers. They summarize what each provider describes publicly; they do not establish equivalent specifications, audited yield, or suitability for a particular PIC.
| Provider | Publicly described options | What to verify for your project |
|---|---|---|
| AIM Photonics | Its PDK page lists active/passive, low-loss, silicon nitride, quantum-flex, and electronic-interposer entries. The page marks some other kits “Coming Soon.” Its wafer services connect to PDK-enabled design, and its ADK adds packaging design enablement. | Confirm the required kit’s present availability and version, its supported devices and EDA flow, and whether the needed packaging configuration is supported. |
| GlobalFoundries | Describes a production silicon photonics portfolio, PDK and reference-flow support, photonics, RF, and advanced-packaging integration, and support for pluggable optics and co-packaged optics (CPO). Its technology page includes vendor-reported generation and device claims. | Check that the process, performance evidence, package, and test flow match the design’s operating conditions; distinguish demonstrated capabilities from roadmap statements. |
| imec | Describes 200 mm and 300 mm silicon photonics platforms and 200 mm and 300 mm SiN options. Its iSiPP200 description includes a validated PDK and potential active-component integration, with full-mask access and selected MPW routes. | Confirm which platform and integration route applies, whether the required technology has MPW access, and the current schedule and eligibility. |
| Tower Semiconductor | In a November 26, 2024 release, announced a 300 mm silicon photonics process as a standard offering alongside its 200 mm PH18 process; the release described PH18 as in high-volume production then. | Ask Tower to confirm current status, capacity, and conditions for a new design; the dated announcement does not establish a customer’s allocation or yield. |
What should you do before committing to a design?
- Write down the system requirements. Specify the devices, integration, wavelengths, performance targets, package, optical and electrical interfaces, and test needs.
- Request the current PDK and process information. Check the exact version, supported devices, models, rules, EDA compatibility, access conditions, and change policy.
- Ask about prototype access. Establish whether an MPW or full-mask route fits the design, then confirm current deadlines, constraints, eligibility, and turnaround.
- Request evidence for critical claims. Ask which figures are measured, demonstrated, production-qualified, or planned, and under what conditions they apply.
- Review packaging and test alongside the PIC. Confirm fiber attach, interfaces, package design, test access, and known-good-die strategy before the layout is fixed.
- Compare written project terms. Get project-specific answers on cost, capacity, lead time, yield definitions, IP and data handling, failure analysis, and qualification.
Where can you learn more about foundry-ready PIC design?
For a design-focused introduction, Cambridge University Press publishes Silicon Photonics Design: From Devices to Systems by Lukas Chrostowski and Michael Hochberg. The publisher describes it as covering design, simulation, testing, fabrication, foundry-ready designs, and PDK use. It was published in 2015, so use a selected foundry’s current PDK documentation for present-day process rules and capabilities.
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