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What Is a Sequence Control Register?

A sequence control register tracks the next instruction address. Its name, address increment and branch behavior depend on the processor architecture.
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A sequence control register (SCR) holds the address of the next instruction in a processor’s instruction sequence. In the teaching model documented by LMU, SCR is another name for the program counter (PC). During ordinary execution, the address advances; a branch replaces it with the branch destination. The exact register name and how far the address advances depend on the architecture.

What does a sequence control register do?

The processor uses the SCR’s address to locate the next instruction to fetch or execute. As a program runs in sequence, the register is updated to point to the following instruction. When control flow changes, such as at a branch, the register receives the destination address instead.

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This makes the SCR a control-flow register, not necessarily a counter that increases by one each time. Its essential role is to identify where instruction processing continues.

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Is the SCR the same as the program counter?

In LMU Institute for Informatics’ educational processor model, the register is labelled “SCR (PC),” treating sequence control register and program counter as names for the same function. The precise label varies across terminology and architectures; for a specific processor, its documentation is the authority on register names and behavior.

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Does the register always advance by one?

No. The next address depends on how the architecture represents instruction locations and on the length of the instruction. LMU’s teaching material notes that byte-addressed instructions can require a larger increment. The historical NCR 304 programming manual describes advancing the address by the instruction’s word length. These examples illustrate why “tracks the next instruction address” is more accurate than “counts up by one.”

How does a branch affect the SCR?

A branch changes the address held in the register to the branch destination, so the processor continues from that location rather than the next sequential instruction. The NCR 304 manual describes this replacement explicitly. Other control-flow instructions may likewise redirect execution according to the rules of their architecture.

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Is “sequence control register” a current standard name?

The exact phrase is not universal. ANSI X3.172-1990’s Dictionary for Information Systems records “sequence control register” as an ISO-deprecated term for “instruction address register.” That is a terminology note from the 1990 dictionary; it does not establish that every contemporary processor uses “instruction address register” as its preferred name.

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The cited material establishes the concept and examples of educational and historical usage, but not how widely current vendor documentation uses “sequence control register.” When identifying a register in a particular CPU, use that architecture’s own documentation.

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