3D chip stacking places dies or wafers above one another and connects them vertically, bringing selected chip functions closer together. It can increase functional density and shorten data paths, helping chip designers pursue bandwidth, performance, power, and footprint goals. It does not make transistors smaller, and it is not a universal replacement for transistor scaling.
What 3D chip stacking means
A conventional chip lays its circuits across a mostly flat silicon surface. In 3D integration, designers place some components above others and link them with vertical electrical connections. The result can put compute, memory, I/O, or other functions closer together than a design spread across a single plane.
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Think of a building with several floors connected by short lifts instead of one building with every room spread over a huge footprint. That illustrates the geometry, not the manufacturing challenge: a real stack must account for heat, power delivery, alignment, interconnects, and production yield.
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- Die or chiplet stacking: separate dies are assembled above one another in a package.
- Wafer-level 3D integration: integration takes place at the wafer level, as in TSMC’s [SoIC overview].
- Transistor-level stacking: transistor device layers are built above one another. This is a distinct device-architecture approach, not simply another name for stacking packaged chiplets.
Why stack chips when planar scaling gets harder?
As computing systems grow, moving data between compute and memory can consume time, energy, and physical area. Bringing selected functions closer and connecting them with dense vertical links gives architects another way to improve a system, alongside improving the transistors in each layer.
Intel describes Foveros as a way to place high-performance logic chiplets above a base die that can contain I/O, SRAM, and power-delivery circuits. In Intel’s 2018 announcement introducing Foveros, the company said: “It will allow products to be broken up into smaller ‘chiplets,’ where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top.” This is Intel’s description of its architecture and intended flexibility.
Shorter connections and denser integration can support higher bandwidth or lower communication costs, while combining functions vertically can help use package area more efficiently. Those are design possibilities, not guaranteed outcomes: results depend on the workload, stack architecture, interconnects, thermal design, and manufacturing process. Stacking complements transistor scaling; it does not mean transistor scaling has ended.
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How the interconnect makes a stack work
Putting dies above one another only helps if they can communicate effectively. The vertical links that carry signals and power are therefore central to the design, not a minor packaging detail.
Intel’s Foveros Direct packaging overview describes stacking chiplets on an active base die with a copper-to-copper hybrid-bonding interface. Intel characterizes the resulting die-to-die connections as high-density and low-resistance. This is one example of how packaging technology can create close, dense connections; it does not establish that every 3D stack uses the same bonding method or achieves the same electrical results.
For another integration model, TSMC describes SoIC as wafer-level 3D IC stacking. Its SoIC overview presents the platform, while its SoIC explainer discusses reintegrating chiplets partitioned from a system-on-chip and using SoIC with other packaging services. The approaches cannot be ranked on a like-for-like basis from these descriptions alone.
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Examples: product packaging versus transistor research
Foveros and Foveros Direct
Foveros illustrates logic-on-logic integration: Intel’s 2018 announcement describes a base die that can carry I/O, SRAM, and power delivery beneath high-performance logic chiplets. Foveros Direct illustrates a more specific interconnect approach, using copper-to-copper hybrid bonding according to Intel’s packaging overview. These are vendor descriptions of architectures and capabilities, not independent comparative performance measurements.
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TSMC presents SoIC as wafer-level 3D integration and describes its role in bringing chiplets partitioned from a system-on-chip back together. The term identifies a platform and integration approach; it should not be treated as a synonym for every kind of chiplet or transistor stacking.
Intel Data Center GPU Max Series
Intel Foundry’s undated technology overview, accessed in 2026, says the Data Center GPU Max Series uses EMIB 3.5D and has more than 100 billion transistors, 47 active tiles, and five process nodes. Those figures describe a heterogeneous multi-die package example. They do not mean all of its transistors are vertically stacked.
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Stacked transistor devices
At IEDM 2023, Intel reported a research demonstration of vertically stacked complementary field-effect transistors with gate pitch down to 60 nanometers. This is a company-reported research result about transistor architecture, distinct from a commercial chiplet package. The announcement does not establish commercial availability.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What limits 3D stacking?
Heat removal
Heat from an upper die has a more difficult path out of the stack. The IEEE’s 3D IC overview identifies thermal analysis as part of stack planning. Designers need to consider where heat-producing functions sit and how heat can escape; vertical density alone does not guarantee a workable design.
Power, interconnects, and integration
A stack must deliver power as well as signals, and its dies must be aligned and connected in a way that works for the intended design and production process. The architecture, bonding or other interconnect method, and manufacturing integration all affect whether the intended density or communication benefits are practical.
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No universal performance or cost figure
There is no single performance gain, energy saving, cost, or yield improvement that applies to all 3D-stacked chips. The cited vendor and engineering descriptions explain approaches and potential benefits, but do not provide an independently verified universal figure or a like-for-like benchmark across Foveros and SoIC.
How to interpret claims about a “3D chip”
When a product or technology is described as 3D-stacked, identify what is actually stacked and where integration occurs. A package may combine many dies or tiles without every die being vertically stacked; a transistor-level research structure is a different claim from a product package.
Quick Recap
- What is stacked? Separate dies or chiplets, wafers, or transistor layers?
- Where does integration happen? During package assembly, at wafer level, or during device fabrication?
- What connects the layers? Is a particular interconnect method stated, or is the description general?
- Which functions are combined? Logic, memory, I/O, cache, and power delivery have different roles.
- What evidence supports the benefit? A vendor’s design intent, a research demonstration, and an independently measured product comparison are not the same kind of evidence.
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