The Tool Desk
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Start with the product’s requirements, not the foundry’s headline node
A process that looks suitable on paper may not meet a particular product’s needs. Compare the destination process against the product’s actual performance, power, area, voltage and device-option requirements, as well as its memory, analog, packaging and any special-process needs. A node name alone does not establish that two processes are interchangeable or that they will deliver equivalent results.
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Ask the candidate foundry for current process specifications and evaluate them against the design and its intended operating conditions. The available sources do not provide a neutral, process-by-process comparison across foundries, so product-specific analysis and current information from each candidate are essential.
Check design enablement before estimating a port
A port depends on the destination process’s own design rules, process design kit (PDK), supported EDA tools and verification flows. Changes can affect layout, extraction and signoff; an existing design flow should not be assumed to transfer unchanged.
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- PDK and rules: Confirm which PDK version and design rules apply to the target process, their maturity, and how updates or rule changes will be managed.
- EDA support: Identify supported tool versions, file formats and flows, and establish whether extraction and signoff results correlate with the destination foundry’s expectations.
- Engineering support: Agree on who will help resolve rule, tool-flow and verification issues, and what design services are available if the internal team needs them.
Foundry-specific rules and tool interoperability are not new concerns: TSMC described process-specific design rules and work with EDA partners on interoperable formats and tool qualification in a 2010 announcement. That announcement illustrates the type of dependency to check; it is not a current list of supported tools or versions. Obtain the present flow and support details directly for the candidate process.
Audit IP and libraries block by block
Do not treat IP portability as a single yes-or-no property of the chip. For each hard macro, memory, standard-cell library, interface block and other licensed component, establish whether it is available for the destination process and whether it has the required assessment or qualification evidence.
- Confirm licensing rights for the new foundry and any restrictions on use, transfer or disclosure.
- Identify what must be re-integrated, revalidated or redesigned, and who owns that work.
- Clarify responsibility for resolving failures at the boundaries between IP, the design and the destination process.
Foundry-specific IP programs can provide useful information, but labels such as “silicon-verified” should not be read as a guarantee for a particular implementation. TSMC states that it does not guarantee silicon-verified IP will work in every design environment or achieve a particular production yield ratio in its IP Alliance terms. Ask the IP owner and destination foundry what the evidence covers and what remains the customer’s responsibility.
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Build a product-level qualification and reliability plan
Qualification of a manufacturing technology is not the same as completed qualification of every customer product designed on it. Map the product’s requirements to the evidence needed for the destination process and for the product itself. Include the planned qualification work, reliability evidence under the intended operating conditions, failure-analysis path, change control and customer acceptance criteria.
TSMC describes a process in which new technologies undergo qualification before transfer to fabs, with quality and reliability systems extending into mass production on its Quality Policy page. This is an example of one supplier’s stated approach, not a universal checklist or proof that a particular product is qualified. Set acceptance criteria and responsibilities with the foundry and the product’s customers.
Ask for comparable yield and reliability evidence
Foundry yield figures are useful only when their scope and conditions are clear. Ask what process maturity and product-relevant evidence are available, and establish whether the data concern the same kind of design, operating conditions and manufacturing stage as your product. For reliability results, clarify the applicable conditions, test scope and failure-analysis process.
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The sources available here do not establish independent, comparable yield or reliability results across foundries. Do not treat one supplier’s process data, qualification statement or IP assessment as evidence of another supplier’s performance, or assume that a process-level result predicts a specific product’s production yield.
Compare the full cost and schedule of the move
Wafer pricing is only one part of the economics. Build a product-specific estimate that accounts for both one-time transition work and the path to stable production.
- Design porting, layout changes and verification or signoff work.
- Mask and prototype-run costs, plus any additional engineering iterations.
- Product qualification and reliability work.
- Potential yield learning and the time and resources needed to reach volume.
- Packaging, assembly and test changes, as well as logistics and capacity constraints.
- Time to volume and the commercial impact of a longer or uncertain ramp.
For scale, the Semiconductor Industry Association reports that the cost of designing a new chip on the latest manufacturing node rose by more than 18 times between 2006 and 2020: about $30 million for a 65nm design in 2006 versus more than $540 million for a 5nm design in 2020. Those are historical, industry-level latest-node design-cost figures—not estimates for moving an existing product, wafer prices or a forecast for a particular design. They illustrate why a transition budget must be tailored to the product rather than inferred from a single industry number. See the SIA’s Chip Design and R&D overview.
Agree on manufacturing visibility and supply operations
Before selecting a partner, establish what information your team will receive, how quickly it will arrive and what agreement governs access. Ask specifically about pilot-lot progress, wafer-yield information, acceptance-test results, quality and reliability data, lot status, assembly and shipping status, and lot traceability. Also clarify capacity assurance, engineering response and any relevant geographic or logistics exposure.
TSMC’s eFoundry service page describes categories of manufacturing and collaboration information available through its own services. That description does not establish that another foundry offers the same data, access or response times; obtain commitments from each candidate in writing.
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Resolve commercial, legal and jurisdictional constraints
A technically feasible port can still be blocked or complicated by business terms. Review existing and proposed contracts, IP ownership and licensing, confidentiality and data handling, export controls, and jurisdiction-specific obligations with the relevant legal and compliance teams. Which rules apply depends on the product, parties and jurisdictions, so these points cannot be resolved from process information alone.
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Use a candidate-by-candidate decision framework
Compare each foundry and process against the same product-specific questions. Record the evidence, assumptions, owner and open issue for each item rather than relying on a broad “qualified” or “compatible” label.
| Decision area | Evidence or commitment to obtain | Question the team must answer |
|---|---|---|
| Technical fit | Current process specifications and product-specific analysis | Does the process meet the product’s performance, power, area, voltage, memory, analog and packaging needs? |
| Design readiness | PDK and rule status, supported EDA versions and flows, extraction/signoff correlation, engineering support | What must change in the design and verification flow, and who will do it? |
| IP readiness | Destination-process availability, assessment evidence, licensing terms and integration responsibilities | Which blocks need revalidation or redesign, and who is accountable for integration issues? |
| Qualification and quality | Product-relevant qualification plan, reliability evidence, failure analysis, change control and acceptance criteria | What evidence will demonstrate that this product meets its requirements? |
| Economics and schedule | Porting, verification, masks, prototypes, qualification, yield-learning and production assumptions | What is the full cost and credible time to volume, including uncertainty in the ramp? |
| Supply and operations | Capacity commitments, traceability, information access, engineering response and logistics plan | Can the supplier support the required volume and provide the operational visibility the team needs? |
| Legal and commercial | Reviewed contracts, IP rights, confidentiality, data-handling and jurisdictional requirements | Can the product and its design data be manufactured and supported under the applicable terms? |
Make the decision at explicit gates
- Screen technical fit: Compare current destination-process specifications with the product’s requirements, and set aside candidates that cannot meet them.
- Prove enablement and IP readiness: Obtain the relevant PDK, rules, supported flows and block-by-block IP status. Estimate the actual rework and validation needed before treating the design as portable.
- Agree on qualification evidence: Define product-level requirements, reliability and qualification work, failure analysis, acceptance and change-control responsibilities.
- Cost and schedule the transition: Include design and verification work, masks and prototypes, qualification, packaging and test changes, yield learning and time to volume.
- Secure operating and commercial terms: Confirm capacity, lot and quality information access, response expectations, logistics, IP rights and legal constraints before authorizing the move.
Proceed only when the evidence and commitments support the product’s requirements and the transition’s economics—not merely because the destination process or wafer quote appears attractive.
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