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What does TSMC 3DFabric mean?
TSMC 3DFabric is the umbrella name for a portfolio spanning wafer-level, frontend stacking and backend packaging technologies. It addresses system-level integration: combining logic, memory, or specialty dies to meet the needs of a particular product. TSMC presents possible goals such as bandwidth, power efficiency, latency, size, and design flexibility, but the result depends on the implementation rather than being guaranteed by the portfolio name.
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The distinctions matter because “3D package” is often used loosely. 3DFabric includes vertical 3D stacking, but it also includes approaches TSMC describes as 2.5D packaging and integrated fan-out. The name therefore refers to a family of technologies, not a promise that every chip in it is stacked vertically.
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| Technology | Role and integration approach | What TSMC describes |
|---|---|---|
| TSMC-SoIC | Frontend, wafer-level 3D stacking | Chip-on-wafer (CoW) and wafer-on-wafer (WoW) schemes for vertically integrating similar or different dies. A SoIC stack can be packaged afterward. TSMC SoIC |
| CoWoS | Backend 2.5D advanced packaging | Integrates multiple system-on-chips and high-bandwidth memory stacks; TSMC identifies CoWoS-S, CoWoS-R, and CoWoS-L variants. TSMC CoWoS |
| InFO | Backend integrated fan-out packaging | A packaging family with derivatives for dense die-to-die integration, including InFO-oS for HPC-oriented applications. TSMC InFO |
What is the difference between a 3D stack and its package?
SoIC describes how dies are joined vertically at the silicon level; it does not necessarily describe the finished package surrounding them. TSMC says a SoIC-integrated chip can be assembled into a conventional package or combined with further 3DFabric services such as CoWoS. In other words, a design can have a 3D die stack inside a larger package whose integration approach is a separate stage.
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CoWoS, by contrast, is identified by TSMC as 2.5D packaging, and InFO is a fan-out packaging family. Both sit within 3DFabric, but neither label should be treated as synonymous with SoIC’s vertical stacking.
How should a designer compare these approaches?
There is no universal ranking: TSMC describes options and intended design goals, not a single best choice for all products. A comparison should start with the physical integration needed, then consider product-specific constraints.
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- Need vertical die integration? SoIC is the portfolio’s wafer-level 3D stacking platform.
- Need to integrate multiple SoCs and high-bandwidth memory? CoWoS is TSMC’s 2.5D packaging family for that kind of system integration.
- Is a fan-out package the relevant integration approach? Consider the InFO family and its derivatives, including the HPC-oriented InFO-oS.
- What must the design optimize? Evaluate die-to-die bandwidth and density, memory integration, footprint, power, signal integrity, application, and manufacturing or implementation constraints together. The best fit depends on the requirements and trade-offs of the specific design.
Where are TSMC 3DFabric technologies used?
TSMC associates its 3DFabric technologies with applications including HPC, AI, cloud and data-center systems, networking, and mobile products. The technologies are intended to support different combinations of performance, bandwidth, power, latency, footprint, and cost or time-to-market needs. Those are design aims, not quantified outcomes that apply to every implementation.
For more context on TSMC’s portfolio, see its 3DFabric overview, CoWoS technology page, and SoIC technology page.
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