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Google’s TPU matrix unit is formally called the Matrix Multiplication Unit (MXU). It performs the multiply-accumulate operations at the heart of matrix processing, making it the main source of a TensorCore’s compute power for matrix-heavy machine-learning work. The MXU is one part of a TPU—not the whole chip or a cloud TPU allocation.
What does MXU mean in a TPU?
MXU stands for Matrix Multiplication Unit. It is specialized hardware inside a TPU TensorCore that computes matrix products using multiply-accumulate operations: it multiplies values and adds the products to partial sums.
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TPUs are application-specific processors designed by Google to accelerate machine-learning workloads. Since many such workloads rely heavily on matrix multiplication, the MXU handles much of the TensorCore’s computational work for those tasks. It is not a general-purpose processor; other parts of the TensorCore handle other kinds of operations.
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How does the TPU MXU work?
An MXU uses a systolic array: a connected grid of multiply-accumulate units. Data moves from one unit to the next in a fixed pattern as the calculation proceeds. Each unit performs its multiplication and accumulation, passing data and intermediate results through neighboring units rather than repeatedly fetching and storing every intermediate value in registers.
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For a matrix product, parameters and input data move from high-bandwidth memory into the computation path. The array produces partial products and accumulates them into the output. This regular, data-moving pattern is efficient for matrix calculations, but it trades away some of the flexibility of general-purpose hardware.
Where the MXU sits in a TPU
A TPU chip contains one or more TensorCores. Each TensorCore includes one or more MXUs, along with a vector unit and a scalar unit. The number of MXUs depends on the TPU generation; for example, Google specifies four MXUs in each TPU v5p TensorCore.
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Therefore, an MXU is a component within a TensorCore, and a TensorCore is a component within a TPU chip. Neither the MXU nor the TensorCore should be mistaken for an entire TPU chip or a cloud allocation.
How MXU size and precision vary by TPU generation
Google Cloud’s TPU architecture documentation, checked on October 7, 2026, lists the following array dimensions. These are generation-specific specifications, not a property shared by every TPU.
| TPU generation | Multiply-accumulator array per MXU |
|---|---|
| TPU v6e and TPU7x | 256 × 256 |
| TPU versions before v6e | 128 × 128 |
Google describes the current MXU as multiplying bfloat16 inputs and accumulating in FP32. Check the documentation for the specific TPU model before applying that precision description to a particular chip.
Google’s account of its original TPU is a separate historical reference, not a specification for current Cloud TPU models. It describes an MXU with 65,536 ALUs arranged in a 256 × 256 array. For that original design, Google reported 65,536 8-bit integer multiply-and-adds per cycle at 700 MHz, or 92 tera-operations per second under its stated counting convention.
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Which workloads benefit most from the MXU?
The MXU matters most when a workload spends much of its time on matrix computations. Google’s introductory TPU guidance identifies matrix-heavy models, large training runs, and large embedding workloads as suitable examples.
TPUs may be a less natural fit, or may achieve low MXU utilization, when work is dominated by other operations. Factors that can limit suitability include:
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- Frequent branching or many element-wise operations.
- Custom operations in the main training loop.
- High-precision arithmetic that does not fit the TPU’s supported or efficient formats.
Why matrix dimensions and compilation matter
XLA compiles a workload graph for TPU execution and tiles matrix multiplication into smaller blocks. Matrix dimensions affect how that tiling uses the hardware; dimensions may be padded, and misalignment with the hardware’s tile sizes can affect utilization.
Google’s introductory guidance discusses these considerations for its documented 128 × 128 systolic array. That is not a universal performance guarantee or a rule to apply unchanged to every TPU generation: behavior depends on the model, compiler, and chip. Consult the guidance for the particular TPU version and workload.
Does a larger MXU mean a faster TPU?
Not by itself. An MXU’s array dimensions describe one part of the chip, not end-to-end performance. A meaningful comparison also depends on numerical precision, the number of MXUs per TensorCore, memory and interconnect design, software support, and the workload being run. An isolated MXU specification cannot establish that a TPU will outperform a GPU or CPU; that requires a controlled comparison on the relevant workload.
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Sources
- Google Cloud: TPU architecture — TensorCore components, MXU dimensions, and precision guidance.
- Google Cloud: Introduction to Cloud TPU — workload fit and matrix tiling guidance.
- Google Cloud Blog: The first TPU — historical specifications for the original TPU.
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