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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →There is no documented, generally stable recipe for the exact combination of Qwen3.8-Flash-Next NVFP4, PLE loading, and B12x in vLLM. NVIDIA documents an NVFP4 deployment on four B200 GPUs using TP4 plus expert parallelism, while vLLM’s B12x MoE backend does not support expert parallelism. Treat those as different deployment paths, not settings to combine. PLE is a major part of the memory requirement: the 51B-parameter N-gram embedding table is placed in host RAM in NVIDIA’s recipe, which specifies at least 51 GB of host memory per worker. NVIDIA’s deployment recipe
What the model requires—and what “stable” should mean
Qwen3.8-Flash-Next is a multimodal ultra-sparse mixture-of-experts model with 125B total parameters and 6B active parameters per token. Its architecture combines Gated DeltaNet (GDN) with Qwen Sparse Attention (QSA), and includes a 51B-parameter N-gram embedding table that the deployment recipe places in host RAM. NVIDIA lists a native 262,144-token context and an extension to one million tokens using YaRN. These model characteristics make GPU count alone an inadequate deployment plan: host memory, PLE residency, attention and MoE kernels, and the request workload all matter. NVIDIA’s deployment recipe
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For this model, “stable” needs to be scoped to what was actually validated. Engine startup, a short text-generation request, long-context generation, multimodal input, concurrency, CUDA graph capture, and prefix-cache behavior are separate outcomes. A successful startup does not establish the others.
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Which deployment path is documented?
| Path | Hardware and parallelism | Checkpoint and PLE | What the source establishes |
|---|---|---|---|
| NVIDIA NVFP4 deployment recipe | Four B200 GPUs; TP4 plus expert parallelism | Inferact/Qwen3.8-Flash-Next-NVFP4; PLE in host RAM, with at least 51 GB host memory per worker |
The deployment recipe specifies MTP3 speculative decoding and an upstream, model-specific vLLM image containing GDN/QSA kernels. NVIDIA notes that this is a third-party container image, not an image NVIDIA distributes. The recipe does not establish B12x compatibility or a stable B12x configuration. NVIDIA’s deployment recipe |
| vLLM H100 validation | Four H100 80GB GPUs; TP4 | Official FP8 checkpoint; PLE CPU offload is recommended to avoid startup OOM | This is an FP8 recipe, not NVFP4 validation. Its reported performance is about 1,430 output tokens/s at concurrency 64 on a random workload with 1,024 input and 256 output tokens; do not attribute that result to NVFP4. The validation did not test a single 262K-token request. vLLM Recipes, updated 2026-09-30 |
| Four-RTX-5090 NVFP4 startup attempt | Four RTX 5090 GPUs; exact parallelism and runtime image are not stated in the issue | NVFP4 attempt; logs show checkpoint and PLE offload loading completed before a worker failed during startup | The issue documents a startup failure reported on September 16, 2026. It does not establish the root cause, a fix, or a successful generation request. vLLM issue #57125 |
| Community GB10/unified-memory reproduction | GB10/unified-memory setup; exact parallelism and workload details are not stated in the reproduction notes | Custom packed 4-bit PLE loader and file-backed mmap; other patches include a persistent output-buffer change for CUDA graph capture | The author reports that mmap freed about 27 GB in that configuration and that built-in CPU offload did not free the same unified-memory pool. These are project-specific claims, not upstream guarantees or a general NVFP4 recipe. Community reproduction notes |
The official NVFP4 path and the H100 FP8 path answer different questions. The former is the documented checkpoint and topology for NVFP4; the latter contains memory guidance for H100 and FP8 performance data. Combining the NVFP4 checkpoint with the FP8 benchmark, or treating the FP8 recipe as proof that NVFP4 works, would overstate the evidence.
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How to plan PLE loading and memory
Use CPU offload where the documented setup requires it
PLE injects N-gram embeddings into the main model. The recipe’s VLLM_PLE_CPU_OFFLOAD=1 setting places the embedding table in host RAM. NVIDIA describes this offload as required for DEP and for TP/TEP on 80GB-class H100 GPUs, where the table alone exceeds available headroom; it may be optional on GPUs with more VRAM per rank. That is recipe-specific guidance, not a universal guarantee for every GPU or quantization layout. vLLM Recipes
Budget at least 51 GB of host memory per worker for the NVIDIA deployment recipe, in addition to GPU memory. If startup fails while loading model weights or PLE, reducing --max-model-len or increasing tensor parallelism are documented memory-pressure mitigations in the vLLM recipe. Increasing TP changes the deployment topology and must still be compatible with the selected kernels and MoE strategy; it is not an automatic fix for every startup failure. vLLM Recipes
Consider mmap only as a project-specific unified-memory workaround
The community GB10 notes describe a packed 4-bit PLE loader and file-backed mmap. The author reports roughly 27 GB freed in that particular configuration and says built-in CPU offload did not free the same unified-memory pool. Do not interpret that figure as a benchmark or expected saving on other systems. The notes also describe a persistent output-buffer change for CUDA graph capture, plus fixes involving a Marlin thread configuration and Mamba/prefix-cache crashes. These are custom patches; the notes do not make them upstream vLLM behavior or prove the whole stack stable for all request types. Community reproduction notes
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Can B12x run this NVFP4 model?
Only evaluate B12x after checking the exact GPU architecture, each quantized layer’s format, activation path, parallelism mode, and vLLM version. vLLM v0.29.0 documents B12x CUDA kernels for NVIDIA SM120 and SM121 systems. Its MoE backend accepts specified NVFP4 or MXFP4 configurations, but does not support expert parallelism. Dense W4A16 layers need another compatible backend, and linear and MoE backend selection can be independent. The documented VLLM_B12X_MOE_FP4_FORCE_A16=1 option forces BF16 activations for FP4 formats. vLLM v0.29.0 B12x documentation
This creates a topology conflict with NVIDIA’s NVFP4 deployment recipe: that recipe uses TP4 plus expert parallelism, while B12x MoE does not support expert parallelism. A B12x attempt therefore needs a compatible non-EP MoE topology and appropriate backend support for the model’s other layer formats; the documentation does not certify that the full Qwen3.8-Flash-Next NVFP4 checkpoint works under those conditions.
The current vLLM CLI reference lists both b12x and flashinfer_b12x, and describes FlashInfer B12x MoE for SM12x hardware, including RTX Pro 6000 and DGX Spark. A backend name in the CLI is not evidence that a particular checkpoint, quantization layout, and end-to-end topology is supported. An NVIDIA developer-forum report associates a community DGX Spark setup with this model family, but it is not an official compatibility certification. vLLM stable CLI reference NVIDIA Developer Forum report
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Troubleshoot by failure stage
Startup runs out of memory
- Confirm that the host has enough RAM for the PLE strategy. NVIDIA’s recipe specifies at least 51 GB per worker for its deployment setup.
- For an H100 80GB setup following the FP8 recipe, use the documented PLE CPU offload setting. The recipe also identifies reduced
--max-model-lenand increased TP as ways to address loading pressure. - Separate model-weight loading from PLE loading in the logs. In the four-RTX-5090 issue, both checkpoint loading and PLE offload loading completed before the worker failed, so that report does not show PLE loading itself as the confirmed cause. Issue #57125
The worker fails after weights and PLE load
Do not assume that changing PLE offload will fix a failure that occurs after those stages complete. The RTX 5090 report does not identify the root cause or establish a general fix. Check the complete stack—GPU architecture, vLLM build, kernels, topology, and startup logs—rather than treating that single report as a diagnosis.
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- Verify that the GPU is in the documented SM120/SM121 class and that the relevant layer’s format is supported by the selected B12x backend.
- Check whether dense W4A16 layers need a different compatible backend, and confirm that the activation path is appropriate. The FP4 activation option is
VLLM_B12X_MOE_FP4_FORCE_A16=1. - Do not use B12x MoE with expert parallelism; the v0.29.0 documentation says that mode is unsupported. Select a supported topology before attributing failure to PLE. B12x backend documentation
Startup works, but inference is unstable or incomplete
Validate the request types separately: begin with short text generation, then test longer contexts, multimodal inputs if needed, concurrency, graph capture, and prefix caching. NVIDIA’s listed native context is 262,144 tokens; extending to one million uses YaRN, for which the deployment documentation advises evaluating quality at shorter contexts before adopting the extension. The vLLM FP8 validation did not test a single 262K-token request, and it is not NVFP4 stability evidence. NVIDIA deployment recipe vLLM recipe
A practical validation checklist
Before calling a deployment stable, record the configuration and the outcome for each workload. Pin the exact vLLM release or commit and the container image; the available NVIDIA recipe specifies a model-specific upstream image with GDN/QSA kernels but identifies it as third-party, so do not substitute an assumed image tag. Then test and report:
Quick Recap
- GPU model, architecture, VRAM per GPU, GPU count, and host RAM per worker.
- Exact checkpoint and quantization format; for NVIDIA’s NVFP4 recipe, the checkpoint is
Inferact/Qwen3.8-Flash-Next-NVFP4. - PLE residency method: GPU, CPU offload, or a specifically documented custom mmap implementation.
- Linear and MoE backends, activation path, and whether the topology uses TP, EP, or both.
- Context setting and whether YaRN is enabled.
- Separate results for engine startup, short text generation, long-context requests, multimodal input, concurrency, graph capture, and prefix-cache behavior.
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