Plan power and grounding immediately after component placement, before routing ordinary signals. This is when you can see how power rails, current capacity, spacing, and signal return paths affect board area and layer count. A four-layer board is a useful starting point for many designs, but no layer count by itself guarantees an EMI compliance pass.
Why plan power routing before signal routing?
Power and ground paths take up physical space and shape the board’s stack-up. Planning them after placement—but before ordinary signal routing—helps expose conflicts while there is still room to adjust component positions, board dimensions, or layer count. James Niemann’s Analog Devices article, published June 23, 2026, recommends deciding the layer count and stack-up early in the layout process.
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Start by identifying demanding circuit groups: high-current loads, high-voltage nets, sensitive analog circuits, and high-speed signals. Each can impose different requirements on trace width, spacing, reference continuity, and decoupling. Power planning is therefore not just a question of where to place supply traces; it is part of deciding whether the proposed board area and layer arrangement can support the whole design.
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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsWhat determines the number of PCB layers?
There is no universal layer count for EMI compliance. Consider the board’s constraints together rather than treating a particular count as a rule:
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- Board area and routing density: A compact outline or many nets may leave too little room for practical routing on fewer layers.
- Current and voltage: Higher current can require wider conductors, while high-voltage nets and safety requirements may require greater separation.
- Power rails: More rails can make it harder to distribute power cleanly, especially when the board has limited copper area.
- Signal references and return paths: High-speed and sensitive signals need a suitable, continuous reference path. A layer plan that forces signals across gaps or changes their reference can undermine the intended routing.
- Decoupling and plane capacitance: The number and arrangement of layers affect where decoupling can be placed and how power and ground are distributed.
- Circuit sensitivity and isolation: Analog, high-speed, and isolation circuits may call for different routing regions or reference arrangements.
- Manufacturing cost: More layers can make routing easier, but the design still has to meet its cost and fabrication constraints.
Use these factors to estimate whether two layers are workable, whether four layers provide a more practical arrangement, or whether the circuit needs additional layers. A layer-count decision should follow the electrical and physical requirements, not a promise that a particular construction will pass a test.
When can a two-layer board work?
A two-layer layout has less freedom to separate power distribution from signal routing. In Niemann’s example, power is generally routed on the top layer and ground on the bottom, with ground routed under or alongside signals where practical. That approach can be constrained by multiple supply rails, limited copper area, and the lack of plane capacitance available in a multilayer arrangement.
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Before committing to two layers, check whether the design has enough room for the required current-carrying widths and voltage clearances while keeping signal return paths continuous. If routing one net forces a reference path away from a sensitive or high-speed signal, the apparent layer savings may come at the expense of a sound layout.
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Why are four layers often a useful starting point?
Four layers often provide more flexibility to arrange signal routing and power and ground references than two layers do. That can help preserve return paths and make dense routing more manageable. Treat four layers as a planning starting point, not as a compliance prescription.
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The supporting Analog Devices documents illustrate why context matters. AN-0971 calls for four layers for the techniques evaluated for its isoPower devices. CN0350 says four layers would improve EMS for its specific circuit example. Neither establishes that every design needs four layers or that four layers guarantee compliance.
Stack-ups can also be tailored by circuit region. In a specific EMC board example, AN-2556 describes a four-layer system-side region and a pseudo two-layer field-side region. That is an example of a design-specific arrangement, not a general construction to copy without evaluating the circuit.
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How to plan the stack-up and route critical signals
- Finish placement and mark demanding nets. Identify high-current and high-voltage routes, sensitive analog connections, high-speed signals, supply rails, and isolation boundaries.
- Plan power and ground. Check conductor widths, spacing, rail distribution, and where each circuit group will connect to its reference or return path.
- Estimate board area and layer needs. Account for routing density, current, voltage separation, number of rails, and the need for continuous references. Revisit placement or the outline if the routes do not fit cleanly.
- Choose a stack-up that supports signal references. Decide which layers will carry signals and which will provide suitable power or ground references. Plan routing directions and transitions so critical signals do not lose their intended return path.
- Route sensitive analog and high-speed nets first. Consider each signal together with its reference, return path, supply delivery, and decoupling. Then route the remaining nets around those critical paths.
- Review the complete route for continuity and spacing. Check that power paths meet current needs, high-voltage spacing remains appropriate, and signal references are not interrupted by gaps or routing choices.
Signal-routing details depend on the design. For example, 50 Ω is a common signaling choice, not a universal requirement for every net. Likewise, general routing directions should not be followed mechanically if doing so compromises field containment or other EMC considerations.
What the design examples do—and do not—show
Application notes can show how a particular circuit was arranged, but their construction details are not universal prescriptions. For instance, CN0350 specifies 10 μF and 0.1 μF decoupling for its AD8608 circuit. Those values belong to that example; choose decoupling for the actual components, power delivery, and layout in your design.
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Layout guidance can help identify risks, but it does not establish that a board will pass a specific compliance test. Applicable requirements and test methods vary with the product and market. Evaluate the finished design against the requirements that apply to it rather than inferring a pass from its layer count or from another circuit’s example.
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