Start with the FPGA’s exact part number, not the toolchain name. For a documented open-source flow, iCE40 chips generally point to Yosys, nextpnr, and IceStorm; ECP5 chips to Yosys, nextpnr, and Project Trellis; and certain Gowin devices to Yosys, nextpnr-himbaechel, and Project Apicula. Support varies by device and hard-IP feature, so a family name alone is not enough to confirm a design will work.
Which open-source FPGA toolchain supports your chip?
FPGA tools are architecture-specific: a synthesis or place-and-route tool may support one family, or even only some parts and features within it. Check the exact device identifier printed in the board documentation or design files, then verify that identifier against the relevant project’s support information.
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The clearest documented hardware-design flows in the project documentation covered here are for Lattice iCE40 and ECP5. Apicula documents a flow for named Gowin devices and boards. These are not interchangeable tool stacks, and a listed target does not automatically mean every peripheral, hard-IP block, constraint, or programming method is covered.
| FPGA family and flow | Synthesis and place-and-route | Bitstream and programming | Important coverage notes |
|---|---|---|---|
| Lattice iCE40: Yosys, nextpnr, IceStorm | Yosys synthesizes the design; nextpnr places and routes it. | IceStorm utilities handle bitstream steps. The nextpnr example uses icepack to produce a binary bitstream and iceprog to upload it. |
YosysHQ’s IceStorm page describes support for iCE40 LP/HX 1K, 4K, and 8K devices and UltraPlus features including DSPs, oscillators, RGB, and SPRAM. It says iCE40 LM, Ultra, and UltraLite are not yet supported. |
| Lattice ECP5: Yosys, nextpnr, Project Trellis | Yosys handles Verilog synthesis; nextpnr handles place and route. | Trellis supplies the device database and bitstream-generation tools. | Trellis says it supports all ECP5 devices. Its status list includes logic slices and carries, distributed RAM, internal interconnect, basic I/O, block RAM, global networks, PLLs, and transceivers. Multiplier support is qualified: manual MULT18X18D instantiation is possible, but inference and more advanced DSP features are not yet supported. |
| Gowin: Yosys, nextpnr-himbaechel, Project Apicula | Apicula’s getting-started flow uses Yosys for synthesis and nextpnr-himbaechel for place and route. | The documented flow includes packing and board programming with openFPGALoader. | Apicula lists supported boards and device identifiers, including Sipeed Tang Nano 9K (GW1NR-LV9QN88PC6/I5) and Tang Nano 20K (GW2AR-LV18QN88C8/I7). Verify the exact board and device against that list. |
These project pages describe available flows and feature status, not a guarantee that every design or constraint will succeed. They do not establish a universal performance ranking across the families.
#1 Best Overall
- Designed for students and beginners looking to understand Digital Logic, fundamentals of FPGAs
- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
- Does NOT ship with micro USB cable
What the main toolchain components do
Yosys: synthesis
Yosys translates HDL such as Verilog into a representation that can be mapped to a supported FPGA architecture. It is the synthesis stage in the documented iCE40 and ECP5 flows and in Apicula’s Gowin getting-started flow. HDL language support and which device primitives can be inferred or instantiated depend on the flow and its supported features.
nextpnr: placement and routing
nextpnr assigns design logic to physical resources on the chip and routes connections between them. Its README lists multiple architectures, but that list is not a single maturity level: Cyclone V, MachXO2, and Xilinx 7-series are labeled experimental. Do not treat those targets as equivalent to the documented iCE40 or ECP5 paths simply because they appear in the same README.
Rank #2
- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
Family-specific tools: device data and bitstreams
IceStorm provides iCE40 bitstream utilities, while Project Trellis provides the ECP5 device database and bitstream-generation tools. For Gowin, Project Apicula documents bitstream tools and a workflow that includes packing. These components are why swapping one family’s tools into another family’s flow is not a safe assumption.
How to choose between IceStorm, Trellis, and Apicula
Choose IceStorm for a supported iCE40 part
The nextpnr FAQ recommends Yosys and nextpnr for Verilog development on Lattice iCE40 when an open-source toolchain is needed. Confirm that the specific part is within IceStorm’s stated support; the documented iCE40 family coverage does not include every variant.
Rank #3
- [FPGA Chip] GW2AR-18 QN88 FPGA Chip containing 20736 LUT4 logic cells and 15552 Filp-Flops.There are 2 PLL in this FPGA chip, and many DSP units supporting 18 bit x 18 bit multiplication
- [Onboard Debugger ] Sipeed Tang Nano 20K Development Board support JTAG for FPGA, USB to UART for FPGA,USB to SPI for FPGA communication, Control MS5351 generate frequency
- [USB2.0 HS interface] The 27MHz crystal generates the clock for HDMI display, onboard MS5351 clock generating chip also provides mutiple clocks.Support Serial communication, high-speed SPI reception.
- [Application scenarios] Tang Nano 20K Open source Development Board supports game console emulators, drives RGB screens, multiple display outputs, 20K LUT4, RISC-V soft-core experiments.
- [Wiki] "dl.sipeed.com/shareURL/TANG/Nano_20K/1_Datasheet";Any after-Sales Privems, Please Contact us by click "Waypondev" store and ask a question or leave the message in our forum by "forum.youyeetoo .com/".
Choose Trellis for ECP5
Trellis documents an open-source ECP5 flow with Yosys and nextpnr, and names ULX3S among development boards confirmed working. Check the feature status against the design’s use of DSPs or other hard IP: for example, manual multiplier instantiation is supported in the stated way, but inference and advanced DSP features are not listed as supported.
Choose Apicula only after checking the Gowin device list
Apicula’s examples cover named boards and device identifiers, rather than establishing blanket support for all Gowin chips. Its getting-started requirements include Yosys, nextpnr-himbaechel, openFPGALoader, and Python 3.9 or later. The board name and device-family options matter in its example commands, so use the instructions for the exact target rather than adapting a command by family name alone.
Rank #4
- The best way to get started with FPGAs: Using a simple board with projects that build on eachother, now anyone can get started with FPGA development!
- Fun peripherals available: With 4 LEDs, 4 push-buttons, 7-segment display, USB connector, a VGA connector, and a PMOD (for expansion) you can have dozens of fun projects available to you out of the box!
- Works with Verilog and VHDL: No matter which programming language you want to get started with, the Go Board will work for you!
- No extra device required: Simply plug the Go Board into a USB port and go! Getting started with FPGAs has never been easier.
- Works with all operating systems: Windows, Mac, Linux
What if your FPGA is a different architecture?
Check maturity as well as the architecture list
The nextpnr README also lists Lattice Nexus, NanoXplore NG-Ultra, and Cologne Chip GateMate. It explicitly labels Cyclone V, MachXO2, and Xilinx 7-series experimental. “Listed” therefore answers only whether a target appears in the project documentation; it does not establish production readiness or full feature coverage.
The Tool Desk
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nextpnr’s documentation says binary bitstream creation for NanoXplore NG-Ultra requires NanoXplore’s Impulse tool. That makes the binary bitstream step dependent on a vendor tool, so this is not a fully open-source end-to-end path as documented.
Best Value
- Digilent Basys 3 Artix-7 FPGA Trainer Board: Recommended for Introductory Users
Use VPR for architecture and algorithm research
Verilog-to-Routing (VtR) and VPR serve a different primary purpose from a board-focused flow for implementing a design on a supported commercial FPGA. The nextpnr FAQ describes VtR as focused on FPGA architecture and algorithm research, and describes VPR as a place-and-route tool with a research focus. If the goal is to research a new FPGA architecture rather than program a supported board, that is the relevant distinction.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Plan the full design-to-board workflow
- Identify the exact device. Record the FPGA part number and board model, then check the family-specific project’s stated support. For Apicula, also match the device identifier and board entry.
- Check the design’s hard-IP needs. Compare required memories, DSPs, PLLs, transceivers, I/O, and other dedicated resources with the project’s documented feature status. Do not assume successful logic synthesis implies support for every hard block.
- Confirm synthesis and implementation inputs. Establish which HDL and device primitives the selected flow accepts, and locate the board’s constraints and pin assignments. The cited project notes do not promise a universal constraints file for every board.
- Trace bitstream creation and programming. Verify which utility generates the device bitstream and how the board is programmed. The iCE40 example names
icepackandiceprog; Apicula’s flow names openFPGALoader. Check whether your particular board needs separate programming hardware rather than assuming a generic JTAG adapter will work. - Check the host setup. Confirm operating system and platform requirements for the exact tools you plan to install. Tool availability can vary by host platform.
- Validate timing and constraints on the real target. Place-and-route success depends on the design and its constraints. Project feature lists are not timing guarantees, and the cited documentation provides no cross-family benchmark that would identify one flow as universally fastest.
Can one package simplify installation?
OSS CAD Suite is a binary distribution that groups tools for RTL synthesis, formal verification, place and route, FPGA programming, simulation, and testing. Its documented components include Yosys, nextpnr architecture targets, IceStorm, Trellis, Oxide, Apicula, openFPGALoader, OpenOCD, and ECP5 programming utilities. It can reduce the work of assembling a tool stack, but it does not expand an architecture’s support or erase the differences between target-specific flows.
Check the current release and host-platform notes before installing. The repository lists GHDL for Linux x64 and Darwin ARM64 among platform-specific qualifications, and says Darwin x64 delivery is planned to stop. A tool’s inclusion in the suite should not be read as proof that every component is available for every operating system.
Quick wins for a faster PC:
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Which flow should you pick?
- Supported Lattice iCE40 part: begin with Yosys, nextpnr, and IceStorm, then verify the exact variant and required features.
- Lattice ECP5: begin with Yosys, nextpnr, and Project Trellis; check hard-IP status and board programming details for your design.
- Gowin board or chip: check Apicula’s supported list for the exact board and device before building around its Yosys, nextpnr-himbaechel, and openFPGALoader flow.
- Experimental nextpnr target: treat the target as experimental and examine what remains dependent on vendor tooling, particularly bitstream generation.
- New FPGA architecture research: consider VtR/VPR’s research-oriented purpose rather than expecting a conventional board-programming flow.
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