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Simulation errors between Electric VLSI and LTspice usually come from a mismatch between what Electric exports and what LTspice expects to read. A schematic may look correct in Electric, but the generated SPICE netlist can still contain unsupported syntax, missing device models, undefined subcircuits, floating nodes, duplicate names, or pin-order problems that prevent LTspice from running the circuit.
These issues are especially common in VLSI workflows because layout-aware design tools, schematic symbols, technology libraries, and SPICE simulators each use their own assumptions about devices, connectivity, and naming. A transistor, power rail, or subcircuit that is valid inside Electric may need explicit model definitions, correct library paths, and LTspice-compatible formatting before simulation succeeds.
A reliable troubleshooting process starts by verifying the Electric schematic, checking export settings, inspecting the generated netlist, confirming that all models and libraries are available, and reducing the design to smaller test cases when errors appear. With a structured approach, most Electric-to-LTspice simulation failures can be traced to a specific netlist, model, naming, or configuration problem and fixed without redesigning the entire circuit.
Understanding the Electric VLSI to LTspice Simulation Flow
The simulation path from Electric VLSI to LTspice is a handoff between two different tools: Electric is used to create and organize the circuit, while LTspice is used to solve the electrical behavior described by the exported SPICE netlist. In Electric, the schematic may look correct visually, but LTspice only sees the text representation generated during netlist export. Most simulation errors occur because something that is obvious in the schematic is missing, renamed, unsupported, or incorrectly described in the exported netlist.
A typical flow starts with building the schematic in Electric using components, pins, wires, exports, and cell instances. Electric then writes a SPICE-compatible file containing devices such as transistors, resistors, capacitors, voltage sources, subcircuits, and connectivity nodes. LTspice reads that file, links any referenced model or library definitions, and attempts to run analyses such as .op, .tran, .dc, or .ac. If any device lacks a model, any subcircuit call lacks a matching definition, or any node name violates LTspice expectations, the simulation may stop before producing waveforms.
The separation between schematic connectivity and SPICE syntax is central to troubleshooting. Electric may allow hierarchical cells, technology-specific devices, global nets, and extracted layout elements that do not automatically translate into a clean LTspice-ready deck. For example, an NMOS device in Electric must become an LTspice-understandable MOSFET line with drain, gate, source, bulk, model name, and parameters. If the exported transistor references a model named nmos, LTspice must be able to find a corresponding .model nmos or a .subckt definition through an included library file.
Typical data passed from Electric to LTspice
- Device instances: MOSFETs, resistors, capacitors, diodes, voltage sources, current sources, and subcircuit calls.
- Node names: nets created by wires, exports, labels, power rails, ground symbols, and hierarchical connections.
- Model references: names attached to transistors, diodes, BJTs, or custom cells that must match definitions available to LTspice.
- Simulation directives: analysis commands such as .tran 10n, .dc, .op, and library includes such as .include filename.lib.
- Subcircuit definitions: hierarchical cells exported as .subckt blocks with ordered pins and internal devices.
One common source of confusion is that Electric can represent hierarchy graphically, while LTspice relies on strict subcircuit syntax and pin order. If a cell symbol in Electric has pins ordered as in, out, vdd, gnd, but the generated or referenced SPICE subcircuit expects out, in, gnd, vdd, the circuit may simulate incorrectly or fail with unexpected floating nodes. Similarly, a supply net named GND in Electric is not always equivalent to LTspice node 0 unless the export settings or symbols map it properly.
A reliable workflow treats the exported netlist as the source of truth before running LTspice. After exporting from Electric, open the generated SPICE file and check that each instance line has the expected number of terminals, that every model name is defined or included, and that ground is represented as node 0 where required. Also verify that analysis commands are present; a syntactically valid netlist without a .tran, .op, .dc, or similar directive may load but not perform the intended simulation.
Practical flow to follow
- Create and save the Electric schematic with clear pin names, power nets, and ground connections.
- Run Electric’s checks to detect disconnected pins, invalid exports, or technology mismatches.
- Export the SPICE netlist using settings compatible with the target LTspice device models.
- Inspect the netlist manually for model references, subcircuit calls, node names, and analysis commands.
- Open the netlist in LTspice, confirm that included libraries are accessible, then run the simulation.
Common LTspice Error Messages and What They Mean
When Electric exports a SPICE netlist and LTspice refuses to simulate it, the error text is usually the fastest clue to the problem. Most failures are not caused by the circuit topology itself, but by mismatches between Electric’s generated netlist and what LTspice expects: missing model definitions, invalid node names, unsupported syntax, unconnected pins, or devices whose symbol parameters were not exported correctly.
Frequent LTspice errors from Electric-generated netlists
| Error message | Common meaning | Where to check |
|---|---|---|
| Unknown subcircuit called in: X… | A subcircuit instance exists in the netlist, but there is no matching .subckt definition loaded. | Library includes, cell names, exported subcircuit names, and .include paths. |
| Cannot find definition of model … | A MOSFET, diode, BJT, or other device references a model name that LTspice cannot locate. | Process model files, .model statements, and NMOS/PMOS model names assigned in Electric. |
| Node … is floating | A net has no DC path to a defined reference or is connected only to capacitive or isolated terminals. | Power rails, ground symbols, transistor bodies, input sources, and unconnected pins. |
| Singular matrix | LTspice cannot solve the circuit equations, often because of floating nodes, ideal source loops, or missing DC bias paths. | Voltage source loops, current source-only branches, capacitors in series, and isolated wells or bulks. |
| Unknown parameter or Questionable use of curly braces | The exported parameter syntax is not valid for LTspice, or Electric emitted a value format LTspice does not parse. | Device width, length, multiplicity, expressions, units, and parameter names. |
| Fatal Error: Missing node(s) | A component line has fewer nodes than LTspice requires for that device type. | Symbol pin mapping, exported ports, transistor source/drain/gate/bulk connections. |
For Electric VLSI designs, model-related errors are especially common. A MOSFET line may look syntactically valid, such as M1 drain gate source bulk nch W=1u L=180n, but LTspice still fails if the model nch is not defined in an included library. The model name used in Electric must match the model name in the technology file or process design kit. For example, if the library defines nmos_180 and pmos_180, but Electric exports NMOS and PMOS, LTspice will report missing models even though the circuit drawing appears correct.
Subcircuit errors usually come from hierarchy. If Electric exports an instance of an inverter as Xinv1 in out vdd gnd inverter, LTspice needs a corresponding .subckt inverter … definition in the same netlist or in an included file. Problems occur when the child cell was not included during export, the cell name was changed, or the port order in the symbol does not match the subcircuit declaration. Case and spelling consistency matter in practice, especially when files are moved between tools and operating systems.
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Node and naming errors often come from legal names in Electric that are awkward or invalid in SPICE. Avoid spaces, punctuation-heavy names, and names that can be confused with numbers or units. Nets named 1, 10u, v(out), or a-b can create confusing parser behavior. Ground is another common source of failure: LTspice expects the global reference node to be 0. If Electric exports ground as gnd without tying it to node 0, the whole circuit may be electrically floating.
- Open the LTspice error log and read the first fatal error before chasing later warnings.
- Search the generated netlist for the exact model or subcircuit name mentioned in the error.
- Confirm that every .include file path is valid from the LTspice working directory.
- Check that VDD, GND, input sources, and transistor bulk terminals are explicitly connected.
- Reduce the design to one failing cell, simulate it alone, then restore hierarchy after it runs.
Warnings should not be ignored, but fatal errors should be handled first. A warning about an unrecognized parameter may turn into an incorrect device size, while a floating-node warning may later produce a singular matrix. The most reliable approach is to treat the LTspice log as a map back to the exported SPICE line, then return to Electric to fix the symbol, port, model, or net name at the source rather than repeatedly editing the generated netlist by hand.
Checking Netlist Export Settings in Electric
When LTspice fails immediately after opening or running a netlist generated by Electric VLSI, the problem is often in the export stage rather than in the circuit itself. Electric must translate its schematic objects, ports, device names, parameters, and hierarchy into SPICE syntax that LTspice can parse. A small mismatch, such as exporting for the wrong SPICE dialect or omitting subcircuit definitions, can produce errors like “unknown subcircuit,” “too few nodes,” “undefined parameter,” or “cannot find include file.”
Start by confirming that the schematic cell you are exporting is the intended top-level simulation cell. In Electric, it is common to have several related cells: schematic, layout, icon, simulation testbench, and extracted views. Exporting a transistor-level block instead of the testbench can leave out voltage sources, input stimuli, load capacitors, or analysis commands. Conversely, exporting a layout-extracted cell without checking its generated device names and parasitics can create a much larger netlist than expected, making LTspice errors harder to isolate.
Export options to verify
- SPICE format or dialect: Select an output style compatible with LTspice. Generic SPICE is usually safer than simulator-specific formats meant for HSPICE, Spectre, or other tools.
- Top-level cell: Make sure the exported cell contains the full simulation environment, including sources, ground, inputs, outputs, and analysis directives.
- Hierarchy handling: Decide whether Electric should preserve hierarchy using .subckt blocks or flatten the design. Preserved hierarchy is cleaner, but every referenced subcircuit must be emitted or included.
- Model inclusion: Check whether Electric writes model statements directly into the netlist or expects LTspice to load them through .include or .lib commands.
- Global nodes: Verify that ground, power, and substrate nodes are exported with names LTspice understands, especially node 0 for ground.
- Parameter output: Confirm that transistor widths, lengths, multiplicity, resistor values, capacitor values, and instance parameters are exported in valid SPICE syntax.
After exporting, open the generated .cir, .spi, or .net file in a text editor before launching LTspice. The first lines should show a recognizable title or comment, followed by device instances, source definitions, model includes, subcircuit definitions, and simulation commands. Look for incomplete lines, empty node names, unexpected special characters, or device instances with missing terminals. For example, a MOSFET line should normally include drain, gate, source, bulk, model name, and dimensions. If the bulk terminal is missing but the selected model expects four terminals, LTspice will stop with a node-count error.
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|---|---|
| LTspice reports an unknown subcircuit | Hierarchy export and missing .subckt definitions |
| Model name is not found | Model library path, .include lines, or device model mapping |
| Ground node is floating or invalid | Ground export name and global node configuration |
| Too few or too many pins on an instance | Symbol-to-device pin mapping and primitive selection |
A practical test is to export the smallest possible version of the design: one transistor, one resistor, or a single inverter with a DC source and load. If that netlist runs in LTspice, Electric’s basic export path is working, and the failure is probably related to hierarchy, models, or a specific cell. If the minimal example fails, correct the global SPICE preferences, library paths, primitive mappings, and ground naming before returning to the full VLSI schematic.
Fixing Missing Models, Libraries, and Device Definitions
Many Electric-to-LTspice failures come from a valid-looking netlist that references devices LTspice does not know how to simulate. Electric can export transistors, resistors, capacitors, voltage sources, and subcircuits, but LTspice still needs matching model statements, library includes, or subcircuit definitions. If the exported netlist contains a MOSFET line such as M1 drain gate source bulk nmos L=…, LTspice must find a model named nmos. If it cannot, errors such as Unknown subcircuit called, Can’t find definition of model, or Unknown parameter are expected.
Start by opening the exported SPICE file in a text editor and searching for every model or subcircuit name used by instance lines. MOSFETs usually begin with M, BJTs with Q, diodes with D, voltage-controlled switches with S, and subcircuit instances with X. For each one, confirm that a matching .model or .subckt definition exists in the same netlist or is pulled in through an .include or .lib statement. The names must match exactly enough for LTspice parsing, and it is safest to keep consistent spelling and case across Electric libraries, exported netlists, and SPICE model files.
Model and library checks
- Confirm the model file path: If Electric exports .include mymodels.lib, LTspice looks relative to the simulation file unless an absolute path is used. Place the model file in the same folder as the exported netlist or use a full path without hidden operating-system substitutions.
- Check process-device names: A schematic transistor labeled NMOS may need to map to a foundry model such as nch_1v8, nfet, or nmos4. Update the Electric device model property or add a wrapper model name in the SPICE file.
- Use the correct LTspice syntax: Some foundry decks contain simulator-specific commands for HSPICE, Spectre, or ngspice. LTspice may reject unsupported parameters, encrypted sections, or conditional library syntax.
- Include all hierarchy dependencies: If a standard cell, pad, op amp, or transistor wrapper is exported as an X instance, the corresponding .subckt block must be available, including any lower-level subcircuits it calls.
Device definitions exported from Electric can also be incomplete when schematic symbols are not tied to SPICE primitives correctly. A resistor symbol, for example, must export as a valid R element with two nodes and a resistance value; a capacitor must export as a C element with a capacitance value; a MOSFET must export drain, gate, source, and bulk nodes in the order expected by the model. If Electric emits a generic subcircuit instance for a primitive device, make sure the library cell has a SPICE template or that an external subcircuit definition is included.
| LTspice symptom | Likely cause | Practical fix |
|---|---|---|
| Can’t find definition of model | Missing or mismatched .model name | Add the correct model deck or rename the Electric model property |
| Unknown subcircuit called | Missing .subckt definition for an X instance | Include the library containing that subcircuit and its dependencies |
| Unknown parameter | Model deck uses syntax LTspice does not support | Use an LTspice-compatible model or simplify unsupported parameters |
| Too few nodes | Symbol pin mapping or SPICE template is wrong | Verify exported pin order and update the Electric component definition |
A reliable repair method is to build a minimal test netlist before simulating the full VLSI schematic. Export or write a one-transistor circuit using the same model name, include the same library file, add a simple voltage source and operating point command, and run it in LTspice. If the small test fails, the issue is in the model include, syntax, or device naming rather than the larger schematic. Once the primitive devices simulate correctly, return to Electric, regenerate the netlist, and keep the library include statements in a stable project folder so repeated exports do not break the LTspice setup.
Resolving Node, Pin, and Naming Conflicts
Many Electric VLSI to LTspice failures come from names that look acceptable in the schematic but become ambiguous, illegal, or inconsistent after SPICE export. LTspice depends entirely on the exported netlist: every device terminal must map to the correct node, every referenced subcircuit pin must appear in the expected order, and every node name must be parseable by the simulator. A schematic can appear visually connected in Electric while the generated SPICE deck contains floating nodes, duplicated labels, or pin-order mismatches that cause incorrect results or immediate simulation errors.
Start by checking node names that Electric exports from arcs, exports, and global signals. Avoid spaces, punctuation-heavy labels, and names that can be interpreted as numbers or expressions. For example, labels such as out+, bias-1, net/clk, or 1V8 may not always behave as intended depending on export style and context. Safer names are simple alphanumeric identifiers with underscores, such as out_p, bias_1, net_clk, and vdd_1v8. Ground is especially sensitive: LTspice requires node 0 as the reference ground. If Electric exports ground as gnd, GND, or another global name without tying it to node 0, LTspice may report floating nodes or produce meaningless operating points.
Pin order and subcircuit consistency
Subcircuit calls are another common source of confusing simulation behavior. In SPICE, a line such as an instance of an inverter does not connect pins by their graphical position; it connects them by the order listed in the subcircuit definition. If Electric exports an instance as X1 in out vdd 0 inv, but the included model defines .subckt inv out in vdd vss, the input and output will be swapped. LTspice may not report this as a syntax error because the netlist is valid, but the simulated circuit will behave incorrectly.
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- Open the exported netlist and find the .subckt definition for each custom cell.
- Compare the exported instance line against the declared subcircuit pin list.
- Verify that Electric’s cell exports use the same names and ordering expected by the SPICE model.
- Regenerate the netlist after changing export names; do not rely on an older LTspice file.
Naming conflicts can also occur when a node, instance, model, and subcircuit share the same identifier. For example, using nmos as both a model name and a cell name can make error messages harder to interpret, especially when Electric emits generated instance names. Keep model names distinct, such as NMOS_180 or PMOS_LVT, and use clear cell names such as inv_x1, nand2_x1, or diffpair_core. LTspice is generally case-insensitive for many SPICE identifiers, so VDD and vdd should not be treated as separate nets for portability.
Practical checks before rerunning LTspice
- Run Electric’s design-rule and network consistency checks to find unconnected pins or accidental shorts.
- Inspect every exported port on hierarchical cells, especially power, ground, bulk, and well connections.
- Search the netlist for generated names such as net@, unconnected, or unusually long hierarchical labels.
- Confirm that all MOSFET terminals appear in the intended order: drain, gate, source, bulk for typical SPICE MOS syntax.
- Make sure global supplies are defined by voltage sources in the top-level testbench, not only by labels.
If LTspice reports a floating node, singular matrix, unknown subcircuit pin count, or unexpected operating point, reduce the schematic to one failing cell plus its sources and loads. Simulate that minimal exported netlist first. Once the cell behaves correctly, rebuild the hierarchy one level at a time. This approach separates true device-model problems from simple node-label, pin-order, and naming mistakes introduced during export.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Validating the Circuit Before Running LTspice
Before launching LTspice, validate the circuit inside Electric VLSI as if the simulator will interpret only the exported text, not the visual schematic. Many simulation failures come from circuits that look connected on screen but produce incomplete or ambiguous SPICE after export. A transistor may appear wired to a rail while its pin is actually connected to a different arc, a bulk terminal may be left floating, or a global power name may not match the name expected by the exported netlist. Catching these issues before LTspice runs saves time and prevents misleading errors such as singular matrix problems, unknown subcircuits, or floating node warnings.
Start by confirming that every device has all required terminals connected. For MOS circuits, this means gate, drain, source, and body terminals must be intentional. In digital CMOS cells, PMOS bodies are usually tied to VDD and NMOS bodies to GND, unless the process model specifies a different well connection strategy. If Electric uses symbols with hidden bulk pins, verify that the symbol, layout, and exported SPICE definition agree. Also check that voltage sources, pulse inputs, capacitors, resistors, and measurement nodes have valid SPICE-compatible values rather than placeholder labels or schematic-only annotations.
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- Run schematic checks: Use Electric’s design-rule and network consistency checks to find unconnected pins, shorted nets, and mismatched ports before exporting.
- Inspect exported net names: Open the generated SPICE file and confirm that expected nets such as vdd, gnd, in, and out appear consistently.
- Verify ground reference: LTspice requires node 0 as the reference ground. If Electric exports gnd or GND, make sure it is mapped to node 0 or explicitly connected through the proper global naming convention.
- Check device parameters: Confirm that MOSFET width, length, multiplier, resistor values, and capacitor values are present and use units LTspice can parse.
- Confirm analysis commands: Ensure the netlist includes a valid .tran, .dc, .ac, or other analysis directive, either from Electric export settings or added manually in LTspice.
It is also useful to validate the hierarchy before simulation. If the design contains subcells, each instance in the top-level schematic must match a corresponding .subckt definition in the exported netlist or included library. Port order matters: a symbol with pins ordered as in, out, vdd, gnd must call the subcircuit in the same order expected by the definition. A swapped supply and output pin may not cause an immediate netlist syntax error, but it can create impossible operating points or unrealistic waveforms. For complex designs, simulate a small cell first, such as an inverter or NAND gate, then move upward to larger blocks.
Finally, perform a quick text-level review of the SPICE file before opening it in LTspice. Look for empty node fields, duplicate instance names, illegal characters, missing .include statements, and components connected to only one node. A clean netlist should have a clear title line, model or library references, valid component lines, at least one source, one ground reference, and an .end statement. If LTspice still fails, reduce the circuit to the smallest reproducible example: one device, one model include, one supply, and one analysis command. Once that minimal case runs, add the remaining Electric-generated hierarchy back in stages until the failing connection or definition becomes obvious.
Step-by-Step Debugging Workflow for Simulation Failures
When a circuit drawn in Electric fails in LTspice, avoid changing many things at once. A reliable workflow is to reduce the problem to one failed assumption at a time: the schematic, the exported netlist, the model files, the simulation command, or the LTspice setup. Start from the Electric cell that represents the intended testbench, not only the device layout or a lower-level schematic. The testbench should include supplies, input sources, load elements, ground, and an analysis directive such as .tran, .dc, or .op.
- Run Electric checks first. Use Electric’s design rule and network consistency checks before exporting. Confirm that all pins are connected as expected, no required exports are missing, and power nets such as VDD, VSS, and GND are not accidentally isolated. If the circuit is hierarchical, descend into each subcell that appears in the failing path and verify that its pins match the symbol used at the parent level.
- Export a fresh SPICE netlist. Regenerate the LTspice-compatible netlist after every schematic edit. Do not rely on an older file in the simulation directory. Open the exported .cir, .sp, or .net file in a text editor and confirm that it contains the expected subcircuits, transistor instances, voltage sources, and analysis commands.
- Check the first LTspice error, not the last one. LTspice may report many secondary errors after one bad line. Open the error log and inspect the earliest reported line number. Then compare that line with the Electric-generated netlist. Common examples include an undefined subcircuit name, an unknown MOSFET model, a malformed parameter, or a node name that LTspice does not accept.
- Verify model and library inclusion. Confirm that every model referenced by an instance has a matching .model or .subckt definition. If the netlist contains devices such as M1 out in vdd vdd PMOS, LTspice must be able to find a model named PMOS. Add or correct .include paths, and prefer simple relative paths when moving projects between folders or machines.
- Run a minimal operating-point test. Temporarily replace complex transient or AC commands with .op. This verifies that LTspice can parse the netlist, load all models, and solve the DC bias point. If .op fails, the problem is usually structural: missing ground, floating node, invalid model, conflicting name, or an impossible source connection.
If the error remains unclear, simplify the design. Simulate a single inverter, current mirror, pass gate, or transistor extracted from the same Electric library and using the same model file. Once that small test works, add hierarchy back one block at a time. This is especially useful for VLSI projects where a top-level failure may be caused by one incorrect symbol pin order or one subcircuit name mismatch several levels down.
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| Debug step | What to confirm | Typical fix |
|---|---|---|
| Schematic check | All pins, supplies, and ground are connected | Add missing exports, wires, or ground reference |
| Netlist review | Instances and subcircuits are written correctly | Correct Electric SPICE export settings |
| Model loading | Every referenced model name exists | Add .include or rename model references |
| LTspice run | First error line is identified | Edit the source of that line in Electric or the model file |
After each correction, export the netlist again and rerun LTspice from a clean state. Keep file names, cell names, model names, and node names simple: letters, numbers, and underscores are safest. When the minimal circuit and the full testbench both simulate, save the working Electric cell, netlist, and model library together so later failures can be compared against a known-good setup.
Frequently Asked Questions
Why does LTspice say it cannot find a model after I export from Electric VLSI?
This usually means the exported SPICE netlist references a device model that LTspice has not loaded. Check the transistor, diode, or subcircuit names in the netlist and make sure the matching .model, .subckt, or library file is included with a valid .include or .lib statement. Also verify that the library path is correct and that LTspice can access the file from the simulation directory.
How do I know if Electric exported a valid SPICE netlist for LTspice?
Open the exported netlist in a text editor and check that it contains proper SPICE elements, node names, model references, power supplies, and simulation commands such as .tran, .op, or .dc. Look for empty node fields, duplicate instance names, unsupported syntax, or missing subcircuit definitions. A quick test is to run a very small known-good schematic first, such as an inverter or resistor divider, and confirm that Electric and LTspice agree on the generated netlist format.
What causes “unknown subcircuit” errors in LTspice after importing an Electric netlist?
An “unknown subcircuit” error means the netlist instantiates a block with an X element, but LTspice cannot find the matching .subckt definition. Make sure the subcircuit name in the instance line exactly matches the name in the library, including spelling and case where relevant. If the subcircuit comes from another Electric cell, confirm that hierarchical netlisting is enabled or that the child cell’s SPICE definition is included in the exported file.
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Pin mismatch errors often happen when the symbol pin order in Electric does not match the expected SPICE subcircuit pin order. Compare the exported instance line against the corresponding .subckt declaration and confirm that drain, gate, source, bulk, power, ground, and signal pins are in the correct order. Also check for unconnected pins, accidental global node names, and power nets named differently between Electric and the LTspice model files.
What should I check first when an Electric-generated LTspice simulation fails?
Start by checking the exact LTspice error log, because it usually points to the failing line number or missing definition. Then verify the Electric schematic for unconnected wires, incorrect exports, duplicated names, and missing power or ground references. After that, inspect the netlist manually, confirm all libraries are included, and simplify the circuit until a smaller version simulates successfully.
Bottom Line
Most Electric VLSI and LTspice simulation errors come down to a few practical issues: an invalid exported netlist, missing or incompatible device models, duplicate or illegal node names, or LTspice not being configured to find the right files. Before assuming the circuit is wrong, check the schematic connectivity, power and ground labels, model includes, device names, and the exact SPICE syntax Electric generated.
A reliable next step is to simplify the design, export a small test netlist, and run it directly in LTspice while fixing errors one at a time. Once the basic flow works, add complexity gradually and keep your Electric libraries, model files, and simulator paths consistent so future simulations are easier to debug.
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