Low-Q Class E amplifiers are attractive when wide bandwidth, relaxed tuning sensitivity, or compact matching networks matter more than narrowband spectral filtering. The challenge is that reducing the loaded Q weakens the network’s ability to reject harmonic energy, so the drain voltage and current waveforms can depart from the familiar idealized Class E shapes and produce stronger harmonic output.
Harmonic suppression in this context is not simply a matter of adding more filtering after the amplifier. The load network, switch capacitance, device parasitics, choke behavior, and output match all participate in waveform shaping, and any change intended to reduce harmonics can also disturb zero-voltage switching, zero-voltage-derivative switching, peak voltage stress, or output power.
Effective low-Q Class E design therefore requires a controlled balance between bandwidth, efficiency, and spectral purity. By understanding how the load network presents impedances at the fundamental and harmonic frequencies, RF power amplifier designers can shape waveforms, manage harmonic terminations, and apply practical filtering methods without sacrificing the switching conditions that make Class E operation efficient.
Class E Operation and the Role of Load-Network Q
A Class E amplifier achieves high efficiency by using the transistor primarily as a switch rather than as a linear current source. The drain or collector voltage is intentionally shaped so that, at the instant the device turns on, the voltage across it is ideally zero and the slope of that voltage is also zero. These zero-voltage switching and zero-voltage-derivative switching conditions reduce turn-on loss and limit stress caused by discharging the device output capacitance through the channel. The load network is therefore not just an impedance transformer; it is an active part of the switching waveform design.
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In the conventional narrowband Class E case, the output network presents a near-resistive load at the fundamental frequency while strongly influencing the impedances seen at harmonics. A series or shunt tuned network, together with the device capacitance and RF choke or finite-feed inductance, determines how much harmonic voltage and current can exist at the switch node. When the loaded Q is high, the network behaves as a selective filter: it passes the desired fundamental component to the load and attenuates much of the harmonic energy created by the switching waveform. This makes the drain waveform closer to the theoretical Class E shape and reduces the burden on any external harmonic filtering.
Load-network Q is commonly understood as the ratio of stored reactive energy to energy delivered per RF cycle, or more practically as a measure of bandwidth. A high-Q network has narrow bandwidth and strong frequency selectivity; a low-Q network has broader bandwidth and weaker selectivity. In RF power amplifier design, low-Q Class E networks are often chosen for wider operating bandwidth, reduced sensitivity to component tolerances, or operation across tunable and frequency-agile bands. The cost is that the network no longer isolates the fundamental as effectively from the harmonic content generated by the hard-switched device.
How Q affects the switch-node waveform
The switch-node voltage in a Class E stage contains a fundamental component plus mulle harmonics required to form the desired non-sinusoidal waveform. The load network sets the amplitude and phase of these components. With sufficient selectivity, the designer can maintain the correct voltage timing at turn-on while keeping most harmonic power from reaching the load. As Q is reduced, the harmonic impedances become less controlled. Some harmonics may see relatively low impedance paths, increasing harmonic current, while others may produce voltage components that distort the drain waveform and shift the zero-voltage switching point.
- High loaded Q: narrower bandwidth, stronger harmonic rejection, more predictable Class E waveform shaping.
- Moderate loaded Q: useful compromise for practical bandwidth while retaining enough harmonic control for efficient switching.
- Low loaded Q: wider bandwidth, greater harmonic leakage, and increased dependence on deliberate harmonic terminations or added filtering.
The role of Q must therefore be considered together with the required output power, device capacitance, supply voltage, operating frequency, and load transformation ratio. A low-Q network can still support efficient Class E operation, but it must be designed with explicit attention to harmonic impedances rather than only the fundamental load resistance. If the harmonic environment is left to chance, the amplifier may still deliver power, but the switch voltage can peak excessively, turn-on loss can increase, and the output spectrum can fail conducted or radiated emission limits.
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Why Low-Q Designs Increase Harmonic Content
In a Class E amplifier, the switch voltage and current waveforms are intentionally non-sinusoidal. The drain or collector voltage is shaped so that the device turns on when the voltage is ideally zero and the voltage slope is also near zero. This switching behavior creates a waveform rich in harmonic energy at the device node, while the output network is expected to pass the fundamental component to the load and attenuate the unwanted harmonics. When the loaded Q of that network is reduced, its ability to discriminate between the fundamental and nearby harmonics becomes weaker, so more of the switch-node harmonic content reaches the load.
A high-Q series resonant output network presents a narrow passband around the operating frequency. At the fundamental, it provides the intended load resistance transformation and phase condition; at harmonic frequencies, its impedance is substantially different, so harmonic currents are restricted or redirected. In a low-Q Class E design, the passband is wider and the impedance slope versus frequency is shallower. The second and third harmonics may see a load impedance that is no longer high enough, low enough, or reactive enough to suppress power transfer. As a result, harmonic currents can flow into the load network instead of being confined to circulating or parasitic paths.
The effect is especially visible in broadband or frequency-agile Class E amplifiers. To maintain operation across a wider frequency range, designers often reduce loaded Q by using lower inductance-to-resistance ratios, broader matching networks, or damping from real component losses and load variation. These choices improve bandwidth, but they also reduce the filtering action that normally smooths the output current into a near-sinusoidal waveform. The switch may still satisfy zero-voltage switching at the design frequency, yet the output spectrum can show elevated second, third, and higher-order components because the load network no longer strongly rejects them.
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Mechanisms that raise harmonic output
- Broader network passband: lower Q reduces attenuation at harmonic frequencies, particularly the second harmonic when the network response is not steep.
- Altered harmonic terminations: the switch sees different impedances at 2f, 3f, and above, which changes the drain-voltage waveform and can increase harmonic voltage swing.
- Higher waveform distortion at the load: harmonic current components that would be filtered by a high-Q network are delivered directly to the load or following match.
- Increased sensitivity to parasitics: package capacitance, device output capacitance, PCB inductance, and transformer leakage can become part of the harmonic path.
Low-Q operation also changes the relationship between harmonic suppression and Class E switching conditions. Harmonic currents are not merely unwanted emissions; they participate in shaping the switch voltage waveform. If a designer adds aggressive harmonic traps or filters without considering the impedance seen by the device, the Class E timing condition can be disturbed. The switch voltage may no longer return to zero at turn-on, or the slope may become excessive, increasing switching loss and device stress. This is harmonic control in low-Q amplifiers must be treated as part of the waveform-design problem, not simply as an output-filtering task.
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A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11Another common source of harmonic growth is operation away from the nominal load or frequency. With lower Q, the circuit is usually expected to tolerate wider excursions, but the harmonic impedances can move unpredictably as the load changes. A load mismatch that is acceptable at the fundamental may create a much more favorable path for second- or third-harmonic power. In practical RF systems, this can lead to spectral regrowth, reduced drain efficiency, and difficulty meeting conducted or radiated emission limits, even when the fundamental output power and DC current appear normal.
Harmonic Suppression Techniques for Low-Q Networks
In a low-Q Class E amplifier, harmonic suppression must be treated as part of the switching waveform design rather than as an afterthought at the output connector. The load network is intentionally broad, so it passes more harmonic voltage and current than a high-Q tuned network. The goal is not simply to short or open every harmonic, but to shape the drain impedance so the switch still sees near-zero voltage and near-zero voltage slope at turn-on while unwanted spectral components are reduced to an acceptable level.
One common method is to add selective harmonic terminations around the main low-Q matching network. A series or shunt resonant trap tuned to the second or third harmonic can provide a low-impedance path for a troublesome component without greatly narrowing the fundamental match. For example, a shunt series-LC trap at 2f0 placed near the drain can reduce second-harmonic voltage swing, while a parallel-resonant element in the output path can block a specific harmonic from reaching the load. These elements should be designed with the device output capacitance, package inductance, PCB parasitics, and matching-network elements included, because the trap frequency can shift substantially at RF power levels.
Another approach is controlled harmonic impedance synthesis. Instead of relying on a simple low-pass or L-network transformation, the designer specifies target impedances at f0, 2f0, and 3f0. The fundamental impedance is chosen to deliver the desired output power and preserve Class E timing, while harmonic impedances are selected to reduce drain-voltage distortion that would increase radiated or conducted emissions. In practice, this often means presenting a high impedance at one harmonic to limit current, and a low impedance at another to clamp voltage, depending on the waveform solution and device capacitances.
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Useful suppression methods
- Second- or third-harmonic traps: narrow selective networks that attenuate the dominant harmonic without forcing a high-Q fundamental match.
- Multi-section output filtering: a low-pass section after the Class E load network can improve spectral purity while leaving the drain-side waveform network relatively broad.
- Transmission-line stubs: open or shorted stubs can provide compact harmonic terminations at VHF, UHF, and microwave frequencies, provided their electrical length includes layout discontinuities.
- Differential or push-pull combining: balanced operation can cancel even-order harmonics at the combiner when device drive and layout symmetry are well controlled.
- Gate-drive shaping: reducing overlap between drain voltage and switch current, and avoiding excessive transition ringing, can lower harmonic generation at the source.
Filtering placed after the main load network is often safer than aggressive harmonic loading directly at the drain, because it is less likely to disturb the Class E switching condition. A post-match low-pass filter can provide strong attenuation at 2f0 and above, but it must be checked for insertion loss, voltage rating, and load-pull interaction. If the filter reflects harmonic energy back toward the amplifier, the reflected impedance becomes part of the drain waveform environment. For this reason, the amplifier, match, filter, and load should be optimized as a single RF network rather than as isolated blocks.
Waveform shaping can also be achieved by adjusting the shunt capacitance and series inductance values away from ideal high-Q Class E equations. In low-Q operation, the textbook values are only a starting point. Small changes in shunt capacitance can reduce drain-voltage peaking or shift the harmonic phase enough to improve spectral performance, while series inductance and load resistance set the slope and curvature of the drain waveform. The best practical designs usually combine moderate drain-side harmonic control with an external low-pass filter, preserving switching efficiency while meeting harmonic limits.
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Tradeoffs Between Efficiency, Bandwidth, and Spectral Purity
Low-Q Class E amplifiers are attractive because they can support wider operating bandwidth, relaxed tuning sensitivity, and tolerance to load or frequency variation. The cost is that the load network no longer behaves like a strong single-frequency selector. More voltage and current energy appears at the second, third, and higher harmonics, and those components can disturb the drain waveform that Class E operation depends on. The designer is therefore balancing three linked targets: high drain efficiency, sufficient modulation or tuning bandwidth, and harmonic levels that meet spectral or system requirements.
Efficiency is highest when the switch turns on with near-zero drain voltage and, ideally, near-zero voltage slope. Harmonic content is not automatically harmful; in fact, Class E operation uses a controlled harmonic-rich drain waveform to shape the switch voltage. Problems arise when the low-Q network allows uncontrolled harmonic impedances. If the second or third harmonic sees an impedance that pulls current at the wrong phase, the drain voltage may not return cleanly to zero at turn-on. The result is overlap between switch voltage and current, increased device dissipation, hotter operation, and reduced power-added efficiency.
Bandwidth improves as loaded Q is reduced because the network impedance changes more slowly with frequency. This helps frequency-agile transmitters, wideband matching, and systems with envelope modulation. However, the same broad response gives harmonics easier paths to the load. A high-Q output tank naturally attenuates out-of-band components, while a low-Q network may need additional harmonic terminations, traps, or a post-amplifier filter. Adding these elements can restore spectral purity, but it may also narrow the usable bandwidth, increase insertion loss, and introduce phase shifts that alter the Class E switching condition.
Typical design compromises
- Lower loaded Q: improves bandwidth and tolerance, but raises harmonic output and makes drain waveform control more dependent on device capacitance and layout parasitics.
- Higher loaded Q: improves harmonic rejection and can simplify spectral compliance, but reduces bandwidth and increases sensitivity to component tolerances.
- External low-pass filtering: reduces conducted harmonics at the output connector, but adds loss and may reflect harmonic energy back into the amplifier if not matched carefully.
- Harmonic terminations: can improve waveform shaping at selected harmonics, but require accurate impedance control at frequencies where package and PCB parasitics are significant.
A practical approach is to treat spectral purity and switching efficiency as simultaneous constraints rather than sequential steps. If a harmonic filter is designed only after the amplifier is tuned for maximum efficiency, its input impedance may change the harmonic loading seen at the drain and move the circuit away from zero-voltage switching. Conversely, if the output network is over-constrained for harmonic suppression, the switch waveform may become more sinusoidal but less efficient. The best result often comes from co-designing the Class E load network, harmonic impedances, and output filter as one RF structure.
The acceptable compromise depends on the application. An ISM-band power stage driving a fixed antenna may tolerate a narrower network and aggressive filtering. A tunable or broadband transmitter may accept slightly lower peak efficiency to maintain output power and switching behavior across frequency. In battery-powered equipment, a one or two percentage point efficiency loss from added filtering may be acceptable if it prevents operation in compression caused by harmonic mismatch. In high-power designs, even small harmonic currents can cause large thermal penalties, so controlled harmonic loading is usually worth the added complexity.
Designers should evaluate tradeoffs using drain efficiency, power-added efficiency, harmonic power at the load, drain peak voltage, and switching loss together. A low second-harmonic level at the output is not sufficient if the drain voltage peak exceeds device rating or if turn-on loss rises sharply. Similarly, excellent zero-voltage switching at the nominal frequency is not enough if the third harmonic violates emissions limits over temperature and load mismatch. Robust low-Q Class E design requires a controlled compromise where the network remains broadband enough for the application while presenting predictable harmonic impedances that preserve the intended switching waveform.
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Harmonic performance in a low-Q Class E amplifier should be evaluated with both time-domain waveform checks and frequency-domain spectral checks. A circuit can show acceptable output power and drain efficiency while still producing excessive second, third, or fifth harmonic energy because the low-Q load network does not strongly reject out-of-band components. The simulation setup should therefore verify the switch-node voltage waveform, switch current waveform, load current spectrum, and delivered power at the fundamental and harmonics under the same operating point.
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Start with a harmonic-balance or periodic steady-state simulation that includes nonlinear device capacitances, package parasitics, PCB interconnect inductance, finite choke impedance, and realistic capacitor ESR. Ideal switch models are useful for initial tuning, but they often underestimate high-frequency harmonic content because they omit output capacitance variation, reverse conduction, transition loss, and bond-wire resonance. In a low-Q design, these details can move a harmonic impedance from benign to problematic with only a small layout or component change.
Simulation checks that should be included
- Drain-voltage waveform: confirm zero-voltage switching and near-zero voltage slope at turn-on. Harmonic suppression must not create a large residual drain voltage when the device switches on.
- Harmonic load impedances: inspect the impedance seen by the transistor at 2f, 3f, and higher harmonics. A Smith chart or impedance table helps reveal whether a trap, shunt capacitor, or matching section is shaping the waveform as intended.
- Output spectrum: measure power at the fundamental and each significant harmonic using the same reference plane used for the load power calculation.
- Parameter sweeps: sweep supply voltage, drive level, load VSWR, temperature, and component tolerances. Low-Q networks are often broadband, but their harmonic terminations may still be sensitive to small shifts.
Transient simulation is especially useful for checking waveform shape. The drain voltage should rise and fall smoothly, without sharp ringing after switch transitions. Ringing near a harmonic frequency often indicates that the network is storing energy in an unintended resonance, which can worsen emissions and increase device stress. A fast Fourier transform of the settled transient waveform can then be compared with harmonic-balance results. Agreement between the two methods gives more confidence that the predicted harmonic levels are not artifacts of the simulator setup.
Bench measurement requires careful attention to reference planes and instrument protection. The amplifier output should be connected to a rated attenuator, directional coupler, or high-power load before the spectrum analyzer. Analyzer input compression can make harmonic levels appear lower than they are, so external attenuation and a known calibration path are preferred. Measure the fundamental power with a power meter or calibrated receiver, then measure harmonics with sufficient analyzer span, resolution bandwidth, and dynamic range. If a low-pass filter is used only to protect the analyzer, its loss and rejection must be de-embedded from the reported amplifier spectrum.
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| Measurement | What it reveals | Common error to avoid |
|---|---|---|
| Drain waveform with high-voltage RF probe | Switching condition, ringing, peak voltage stress | Using a probe with excessive capacitance at the drain node |
| Output spectrum | Second, third, and higher harmonic power | Allowing analyzer compression or ignoring attenuator calibration |
| Load-pull or impedance tuner test | Sensitivity to harmonic terminations and load mismatch | Testing only at a perfect 50-ohm load |
Correlation between simulation and measurement is usually improved by extracting the actual PCB layout parasitics and measuring passive network values at RF, not just at low frequency. Capacitor self-resonance, inductor Q, pad capacitance, and via inductance can all alter harmonic paths. When measured harmonics exceed prediction, update the model with measured S-parameters for traps, filters, bias feeds, and matching sections. This closed loop allows harmonic suppression to be adjusted while preserving the Class E drain waveform and maintaining the desired low-Q bandwidth.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Practical Design Guidelines and Component Considerations
For low-Q Class E amplifiers, harmonic suppression should be treated as part of the initial load-network synthesis rather than as an afterthought. Start by defining the required output power, drain supply voltage, operating frequency, target bandwidth, and allowable harmonic levels at the antenna or system output. From these limits, choose a loaded Q that provides the needed bandwidth while still allowing the drain waveform to approach zero-voltage switching and zero-voltage-slope switching at turn-on. Very low loaded Q values can be attractive for wideband operation, but they increase harmonic current flow and make the switch voltage waveform more sensitive to device capacitance, package inductance, and load variation.
A practical approach is to design the fundamental load impedance first, then add controlled harmonic terminations where they provide the most benefit. The second and third harmonics usually dominate the spectral problem in low-Q Class E stages, so their impedances should be examined explicitly in simulation. A shunt capacitance at the drain, the series resonant output path, and any matching network after the amplifier all contribute to these terminations. Small changes in series inductance, shunt capacitance, or matching-network topology can shift harmonic voltage peaks substantially, even when the fundamental output power changes only slightly.
Component selection priorities
- Drain shunt capacitance: Include transistor output capacitance, package capacitance, PCB parasitics, and any external capacitor. Using only the data-sheet capacitance at one voltage can lead to incorrect timing because MOSFET and GaN device capacitances are voltage dependent.
- Series inductors: Use parts with adequate self-resonant frequency, low AC resistance, and sufficient current rating. At VHF and UHF, a physically smaller inductor is not always better if its Q collapses near the second or third harmonic.
- Capacitors in the RF path: Select low-loss RF capacitors with stable dielectric behavior. C0G/NP0 parts are preferred where practical; high-K ceramics can introduce loss, voltage-dependent capacitance, and temperature drift.
- PCB layout: Keep the drain loop compact and make the return path deliberate. A few millimeters of trace inductance can act as an unintended harmonic tuning element.
- Output filtering: Place low-pass or harmonic-trap elements where they do not disturb the impedance required at the switch. A filter that looks benign at the output connector may present a harmful reactive load at the drain through the matching network.
When adding harmonic suppression, avoid forcing a harmonic short or open at the drain without checking the switching waveform. In a Class E stage, harmonic impedances are not merely spectral filters; they shape the drain voltage and current trajectories. A second-harmonic trap may reduce radiated content but also increase peak drain voltage or cause nonzero voltage at turn-on. Similarly, aggressive low-pass filtering can improve conducted emissions while increasing circulating current and reducing efficiency. The safest design method is iterative: tune the fundamental load for power and switching conditions, adjust harmonic impedances, then recheck drain voltage, switch current, output power, and device stress over supply, temperature, and load mismatch.
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- Parameters: DROK audio amplifier board working voltage is DC 5V, output power is 5W (2Ω 5V)/3W (4Ω 5V) / 1.8W (8Ω 5V). Input method is monaural input.
- Artificial Material: this New-designed mini power amplifier is made of noble black immersion gold circuit board, imported KEMET speaker capacitor, large-capacity filter capacitor for channels. Besides, we customized black copper terminal blocks and gold-plated audio input terminal blocks for this new amplifier module.
- High Performance: the digital amplifier module is with high efficiency of over 90%, general harmonic distortion noise is less than 10%, low quiescent current and noise suppression.
- Safe Protection: the class D dual-channel amp board is designed with input reverse connection protection, short circuit protection, over heat protection; what's more, EMI is allowed to pass.
- Additional Function: it is available to connect amplifier type to choose different function (MODE: high electricity level is Type D, low electricity level is Type AB. Factory defaults high electricity level); available to add an external Shutdown (SD: the chip will be Shutdown at low electricity level, factory default high electricity level.
Bench validation should use both spectral and time-domain measurements. A spectrum analyzer with suitable attenuation and filtering verifies harmonic levels, while a high-bandwidth voltage probe or calibrated RF sampling method helps confirm that the drain waveform still meets Class E timing. Designers should also measure efficiency at several output frequencies across the intended band, not just at the center frequency. In production-oriented designs, allow trim range for the shunt capacitance, series inductance, or post-match filter because transistor capacitance spread and PCB tolerance can move the optimum point. The most robust low-Q Class E amplifiers usually combine moderate harmonic filtering, controlled harmonic terminations, high-Q RF components, and layout discipline rather than relying on one sharply tuned suppression element.
Frequently Asked Questions
Can a low-Q Class E amplifier still meet the standard zero-voltage switching condition?
Yes, but the load network must still present the correct impedance at the switch drain at the fundamental frequency. Low-Q operation broadens the network response, so harmonic impedances can more strongly affect the drain waveform and disturb the voltage and slope at turn-on. Designers usually verify zero-voltage switching and near-zero voltage slope in time-domain simulation after adding any harmonic suppression elements.
Why does reducing loaded Q increase harmonic output in a Class E amplifier?
A high-Q output network strongly filters the switching waveform and mainly passes the fundamental component to the load. When loaded Q is reduced, the network attenuates second, third, and higher harmonics less effectively, so more of the switch-generated harmonic energy reaches the output. The drain waveform also becomes more sensitive to harmonic terminations, which can reshape voltage peaks and current timing.
What is the safest way to suppress harmonics without ruining Class E efficiency?
The safest approach is to control harmonic impedances while preserving the required fundamental load impedance seen by the switch. Common methods include adding a low-loss output low-pass filter after the matching network, using targeted traps for dominant harmonics, or shaping the matching network so it presents high or low impedances at selected harmonic frequencies. Each added element should be checked for its effect on drain voltage peak, switching loss, and device stress.
Should harmonic filtering be placed inside the Class E load network or after it?
Filtering after the Class E load network is often easier because it can reduce conducted harmonics while leaving the switch’s fundamental load condition mostly unchanged. However, the filter input impedance at harmonic frequencies can reflect back through the matching network and still alter the drain waveform. For compact or broadband designs, designers often co-design the Class E network and harmonic filter rather than treating them as independent blocks.
How should I verify harmonic suppression in a practical low-Q Class E design?
Use harmonic-balance or transient simulation to inspect drain voltage, switch current, output spectrum, and power-added efficiency across frequency, supply voltage, and load variation. In the lab, measure harmonics with adequate attenuation, calibrated cables, and a spectrum analyzer or receiver that will not be overdriven by the fundamental. Also confirm that the amplifier still maintains safe drain voltage peaks and acceptable efficiency after the harmonic filter is connected.
Bottom Line
Low-Q Class E amplifiers can deliver compact, broadband, and efficient RF power, but the reduced filtering makes harmonic control a central part of the design rather than an afterthought. Suppression comes from shaping the switch waveform, choosing a load network that presents controlled impedances at key harmonics, and preserving the zero-voltage and near-zero-slope switching conditions that make Class E efficient.
The best next step is to co-design the switch, shunt capacitance, series network, and harmonic terminations using simulation and load-pull or harmonic-balance verification, then confirm the drain waveform and spectrum on hardware. Aim for the lowest harmonic content that meets system limits without adding so much filtering or mistuning that efficiency, voltage stress, or Class E operation are compromised.
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