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The procedure below is device-specific where the documentation supports it and deliberately avoids treating one pinout, supply arrangement, clock ratio, or response definition as universal. The MF10-N and TLC04 are worked references, not interchangeable wiring templates.
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Why the clock must be measured as part of the filter
A switched-capacitor filter (SCF) emulates resistors by moving charge with a clock. Changing the clock changes the effective resistance and therefore moves the filter’s cutoff or center frequency. The circuit is also a sampled-data system: signals near or above one-half of the relevant sampling rate can alias, and clock energy can appear at an output as ripple or feedthrough.
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- The clock at the IC pin, not merely the signal-generator setting, is a measurement variable.
- The expected frequency landmark must come from the selected IC’s data sheet. A low-pass cutoff, a band-pass center frequency, a notch frequency, and a high-pass transition are not interchangeable definitions.
- Input spectrum, clock quality, output loading, clipping, and probing can all change the result you observe.
Texas Instruments gives useful family-level context in Basic Introduction to Filters—Active, Passive, and Switched-Cap, Rev. A: “Typical center-frequency accuracies are normally on the order of about 0.2% for most switched-capacitor ICs, and worst-case numbers range from 0.4% to 1.5% (assuming, of course, that an accurate clock is provided).” Those figures describe broad expectations, not a guaranteed specification for your device.
Collect the device facts before connecting power
Record the exact part and test configuration
Write down the complete part number, package, data-sheet revision, intended filter function, section or channel, supply arrangement, external resistor values, clock mode, expected output, and load. A dual or universal IC may expose several outputs at once; identify the one that corresponds to the configuration you are actually testing.
Use the current data sheet to find:
- Allowed supply rails, absolute maximum ratings, power-up requirements, and reference or virtual-ground connections.
- Clock logic threshold, amplitude, allowable frequency, duty-cycle limits, and any mode-pin truth table.
- The clock-to-cutoff or clock-to-center ratio, including tolerance and any dependence on external resistor ratios.
- Input and output common-mode range, maximum signal swing, output-current or load limits, and whether a buffer is required.
- The data sheet’s definition of cutoff, center frequency, bandwidth, quality factor, passband gain, or notch depth.
Do not infer a pinout or supply topology from a different SCF. Even parts from the same manufacturer and family can use different references, clock levels, ratios, and output constraints.
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Use the equation printed for the selected mode. If the data sheet gives a simple ratio, calculate the expected landmark as the measured clock frequency divided by that ratio. If resistor ratios or multiple clock modes appear in the equation, use the actual fitted values and selected mode rather than a nominal default. Keep the calculation with the test record, including the clock tolerance and resistor tolerances used.
For a universal filter, calculate the expected value separately for each configured section and response. A second-order band-pass output, for example, requires a center-frequency and bandwidth expectation; a low-pass output requires a cutoff definition and passband reference.
Choose a documented device reference
The following devices illustrate why the data sheet must control the setup.
| Device | Documented function or ratio | Published accuracy or range | Bench implication |
|---|---|---|---|
| MF10-N | Dual universal filter with separate high-pass/notch/all-pass, band-pass, and low-pass outputs; clock and, in some configurations, external resistor ratios set the response. | Texas Instruments reports ±0.6% clock-to-center-frequency ratio accuracy, operation from 0 to 70 °C, and operation up to 30 kHz on its product page. | Choose the section, output, resistor network, and clock mode first. Use the full MF10 data sheet, Rev. C for equations and limits. |
| TLC04 | Fourth-order Butterworth switched-capacitor low-pass; 50:1 clock-to-cutoff ratio under the documented configuration. | ±0.8% ratio error; 0.1 Hz to 30 kHz cutoff range under the stated ±2.5 V supply condition. | A clock at 50 times the desired cutoff is the starting expectation, not a substitute for checking the exact operating conditions. |
| TLC14 | Related fixed-function family member using a 100:1 clock-to-cutoff ratio. | ±1% ratio error listed in the family information. | Do not use the TLC04 50:1 setting when testing a TLC14. |
The MF10-N product information identifies the device as active as accessed on October 13, 2026. The TLC04ID ordering page showed the part out of stock on that date; stock status can change and is not a performance specification.
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Build the bench setup without assuming a universal pinout
Power, reference, and grounding
Set current-limited supplies to the exact rails required by the data sheet. Connect every supply bypass capacitor, analog ground, digital ground, and reference or virtual-ground node shown in the manufacturer circuit. Keep the reference node at the specified potential; it may not be interchangeable with earth ground.
Plan probe and generator returns before switching on. A grounded oscilloscope probe can short a floating reference or a non-ground output. If the reference is not at earth potential, use an appropriate differential measurement method or reconfigure the circuit so the instrument return is safe.
Clock source and verification
Use a clock source that reaches the specified logic level and frequency range at the IC pin after cable and termination losses. Measure the waveform directly at that pin with a suitable probe. Check frequency, high and low levels, duty cycle, overshoot, ringing, and the return path. Record the actual frequency rather than relying only on a generator display.
For the MF10-N, the data sheet discusses 50/100/CL clock-mode behavior and states that duty cycle should be close to 50%, especially above 200 kHz, so internal operational amplifiers have maximum settling time. Confirm the selected mode and level-shift arrangement in the device data sheet before applying a clock.
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Analog source, load, and instruments
A practical setup normally needs a sine-wave source with enough frequency range, a way to generate and measure the IC clock, and an oscilloscope or frequency-response instrument. These are functional requirements, not a prescription for a particular instrument model.
- Use a low-distortion sine source and begin with a small amplitude well below the data sheet’s input and output swing limits.
- Terminate or buffer the source as the circuit requires. Include source impedance in the test record.
- Apply the specified output load. If the output is unloaded during one test and terminated during another, treat them as different measurements.
- Use short, sensible signal and clock returns. Keep the high-speed clock route away from the analog input and output where practical.
- Use bandwidth limiting, shielding, or differential probing when instrument noise obscures the response.
Step-by-step bench procedure
1. Create a test record
Before power-up, make a table with fields for date, operator, full part number, package, data-sheet revision, board identifier, supply rails, ambient temperature, filter mode, section, resistor values, clock mode, intended load, input amplitude, sweep frequencies, measured clock frequency and duty cycle, and instrument bandwidth settings. This prevents a plausible-looking trace from becoming impossible to reproduce.
2. Derive the predicted landmark
Enter the actual resistor values and the intended clock frequency into the data-sheet equation. Write the predicted cutoff, center frequency, bandwidth, or notch frequency beside the equation. Include the ratio tolerance and the clock-source accuracy. If the part’s documentation does not define a single equivalent “cutoff” for your chosen output, state which response point you will report instead.
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3. Configure the filter
Install the specified resistors, straps, mode pins, and reference connections. For a universal device, verify each jumper against the truth table rather than assuming that a familiar low-pass arrangement applies. Check for solder bridges, wrong resistor decades, and omitted bypass capacitors with power removed.
4. Power up with the signal disabled
Use a current limit appropriate to the device. Confirm each rail at the IC pins and note supply current. An abnormal current draw, a reference node at the wrong voltage, or a rail that collapses is a stop condition; remove power and correct the wiring before enabling the clock or signal.
5. Verify the clock at the IC
Enable the clock and measure it at the device pin. Confirm frequency, duty cycle, logic swing, and waveform integrity against the data sheet. Check that the selected clock mode pin is at the intended logic state. Record the measured frequency for every sweep condition.
6. Establish a low-level baseline
Apply a sine wave well inside the expected passband or around the expected center frequency, at a small amplitude. Observe input and output simultaneously. Look for a stable waveform, plausible gain, excessive DC offset, oscillation, clipping, or a clock-rate staircase. If the IC has multiple outputs, probe the output associated with the configured function.
7. Sweep the analog frequency
Hold clock, supplies, configuration, input amplitude, and load constant. Sweep across the full intended range, using wider steps where the response is flat and dense steps near the expected corner, center, notch, or band edges. At each point record:
- Signal frequency.
- Measured input amplitude at the IC pin.
- Measured output amplitude and, where needed, phase.
- Clock frequency and any visible clock-related component.
- Supply rails, load condition, and oscilloscope bandwidth or detector settings.
Calculate voltage gain as Vout/Vin and gain in decibels as 20 × log10(Vout/Vin). Use the data sheet’s response definition for the reported landmark. A low-pass result might use the specified passband-relative point; a band-pass result needs center frequency, lower and upper frequencies, bandwidth, and preferably Q; a notch result needs notch frequency and residual depth.
8. Repeat with a second clock
Choose a second allowed clock frequency while leaving supplies, resistor values, input amplitude, and load unchanged. Measure the new clock at the IC pin, repeat enough of the sweep to locate the shifted response, and compare the shift with the device’s specified ratio or resistor-dependent equation. This isolates clock tuning from other changes.
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9. Save raw evidence
Save scope screenshots or exported data showing the clock and analog waveforms, the sweep table, supply readings, and the exact configuration. Report resolution and uncertainty. If the frequency step is 1% and the landmark moves less than one step, do not claim a more precise agreement.
How to interpret the measured response
Separate ratio error from clock error
If the measured frequency is wrong by approximately the same percentage as the clock is wrong, correct the source setting or use the measured clock in the calculation. A remaining error after using the measured clock can come from the IC’s ratio tolerance, resistor tolerances, temperature, loading, or the way the response landmark was extracted.
Use the right response metric
| Filter output | Record | Common mistake |
|---|---|---|
| Low-pass | Passband gain, defined cutoff, stopband slope, and any clock-related spur. | Calling the first visible roll-off point the cutoff without using the data-sheet definition. |
| Band-pass | Center frequency, peak gain, lower and upper band edges, bandwidth, and Q. | Reporting only the peak frequency and ignoring bandwidth or gain. |
| High-pass | Passband gain, transition landmark, low-frequency attenuation, and phase if relevant. | Comparing a high-pass transition with a low-pass cutoff convention. |
| Notch | Notch frequency, minimum output, surrounding gain, and residual clock feedthrough. | Mistaking a clock spur or measurement-floor artifact for notch depth. |
Check clock tuning
The frequency shift should follow the documented clock relationship when every other variable remains fixed. For example, a TLC04 configured under its documented conditions uses a 50:1 clock-to-cutoff relationship, while the TLC14 family information lists 100:1. The MF10-N requires the selected mode and, in some configurations, resistor ratios to be included in the calculation.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Sampled-data effects and common failure modes
Aliasing
The MF10-N is a sampled-data filter whose sampling frequency equals its clock. An input component above one-half that sampling frequency can fold into a lower apparent frequency. A sweep can therefore show an unexpected high-frequency rise that is not a failure of the intended analog response.
Limit the source spectrum when the test objective requires it. Use a clean sine wave, remove broadband generator noise, and consider an input anti-alias filter. When documenting a result, state the clock and the highest input frequency so another engineer can judge whether aliasing was possible.
Clock steps and feedthrough
Clock-rate steps can appear at an output, and a clock component can couple directly into the analog path. Texas Instruments notes that an output RC low-pass can smooth clock-rate steps when appropriate; adding one changes the measured loading and bandwidth, so document it. Do not count a clock spur as desired filter output.
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The same overview gives broad context of clock feedthrough on the order of 10 mV peak-to-peak for switched-capacitor filters. Treat that as a family-level warning, not an MF10-N or TLC04 limit.
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Clipping, offset, and high-Q gain
Reduce the input amplitude if the output approaches a supply rail or develops flattened peaks. The MF10-N data sheet warns that clipping changes gain and can change both fO and Q. Check the DC operating point as well: an offset can consume swing even when the sine-wave amplitude appears modest.
Noise and grounding
First separate DUT noise from source, supply, probing, and instrument noise. Disconnect or reduce the input while watching the output, then check the clock and supply rails independently. Texas Instruments gives typical switched-capacitor output noise of 100 to 300 μVrms over a 20 kHz bandwidth as broad context; use the exact IC data sheet for a device-specific noise limit.
Wrong frequency or no response
- Measure the clock at the IC pin, not at the generator connector.
- Recheck the selected ratio or mode pin.
- Verify resistor values, orientation, and reference connections.
- Confirm that the probe is on the intended output section.
- Check that the input and output are within common-mode, swing, and load limits.
- Repeat at a low input amplitude to rule out clipping.
Comparing SCF choices before a bench test
Do not choose a device solely because it is described as switched-capacitor. Compare the following axes for the exact application:
- Filter function and order: fixed-function fourth-order response versus a configurable second-order building block, for example.
- Clock-to-corner or clock-to-center ratio and its tolerance.
- Usable frequency range and temperature range.
- Supply rails, reference arrangement, clock logic level, and duty-cycle requirements.
- External resistor or mode-pin requirements.
- Output swing, load capability, gain, and susceptibility to clipping.
- Noise, clock feedthrough, aliasing behavior, and required input bandwidth limiting.
- Current availability and the status of the exact package and orderable part.
The MF10-N can provide several classical responses and its two sections can be cascaded for up to fourth-order functions, but that flexibility adds configuration checks. The TLC04 is a fixed-function fourth-order Butterworth low-pass with a documented 50:1 ratio under stated conditions. A Texas Instruments application note, The Davies Sinusoidal Generator (October 2022), uses the TLC04 as a tracking harmonic filter clocked at 50 times the desired corner frequency. That example demonstrates clock tuning; it is not a universal acceptance procedure.
Report results so they can be reproduced
A useful report contains more than a screenshot of a Bode plot. Include:
- Exact part number, package, board revision, and data-sheet revision.
- Supply voltages, reference voltage, ambient temperature, and measured current.
- Filter section, output, mode pins, resistor values, and output load.
- Clock frequency measured at the IC, duty cycle, logic levels, source termination, and probe method.
- Input frequency, amplitude measured at the IC, source impedance, and any input bandwidth limit.
- Output amplitude, gain calculation, phase method, and instrument bandwidth.
- Predicted and measured response landmarks, with the extraction rule used.
- Observed spurs, clipping, DC offset, noise floor, aliasing precautions, and uncertainty.
When a value is not established by the device documentation or your measurement resolution, say so explicitly. “Not resolved with a 1% frequency step” is more useful than a false precision claim.
When the setup should be stopped
Remove power if a rail collapses, current rises unexpectedly, the reference node moves outside its allowed range, the IC or output load overheats, or the clock exceeds the documented amplitude or frequency. Correct the wiring and repeat the power-off inspection. Do not compensate for an unsafe or out-of-spec condition by reducing the oscilloscope scale or hiding a clipped waveform.
A valid switched-capacitor filter test is therefore a controlled experiment: identify the exact device, configure it from its own data sheet, measure the clock at the pins, sweep a known analog signal, and interpret the response using the manufacturer’s definitions. That method distinguishes true filter behavior from clock error, aliasing, feedthrough, clipping, and bench artifacts.
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