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Keep an AI agent away from shared or authoritative chip-design files until its access is technically restricted, its proposed changes have passed the project’s checks, and a named person has approved any consequential action. A prompt asking an agent not to write files is not a safeguard: permissions must be enforced by the surrounding system, and the agent’s output must be treated as unverified.
How do I stop an AI agent from changing my RTL?
Start by making the agent’s permitted actions narrower than the task’s full design workflow. In the first stage, let it inspect only the files and data needed to answer the question. If it needs to suggest a change, have it produce a patch in an isolated branch or disposable workspace—not edit the shared project directly.
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Enforce that boundary outside the model, through the application, operating system, scheduler, API gateway or policy service that mediates access. The Australian Signals Directorate’s 2026 harness guidance puts the principle plainly: “Do not rely on model safety controls instead of harness-enforced controls.” A harness connects a model to tools and data and enforces permissions and actions; it is not secure merely because it is called a harness.
Define the boundary before the agent runs. Name the design, data and technical owners, as well as the person authorized to approve changes. Specify which project paths, tools, versions, operations and network destinations are allowed, and which actions are prohibited. Keep proprietary, export-controlled or otherwise restricted design data out of an AI service unless the data owner and responsible institution have approved that exact service and workflow.
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The U.S. Department of Energy’s GEAR guidance states: “A prompt such as ‘never delete files’ is not an access control.” A read-only instruction in a prompt cannot prevent a tool with write permissions from overwriting or deleting a file.
Can an AI coding agent safely access an EDA project?
It can be given bounded access, but “access” should not mean unrestricted access to the project, shell, network and EDA toolchain at once. Assign permissions by task and stage, and use external controls to enforce them.
| Stage | Agent’s permitted role | Control and expected result |
|---|---|---|
| Inspect | Read only the approved project paths and inputs. | Block writes and access outside the task boundary; the agent can explain or analyze, but cannot alter project files. |
| Propose | Generate a patch or script in an isolated branch or disposable workspace. | Keep the proposal separate from shared or authoritative design data so it can be inspected and tested before acceptance. |
| Validate | Run only approved tools and checks against the proposed artifact. | Allow-list verified tools and versions; record tool use and restrict permissions if behavior departs from policy. |
| Accept | No autonomous authority to merge, overwrite, delete or change permissions. | Require explicit approval from a named, qualified person before a consequential project change. |
Use trusted, verified components and a curated allow-list for tools and integrations. Separate reading, proposing and acting responsibilities where practical. Unexpected behavior is a reason to restrict access and investigate, not to grant the agent broader permissions so it can continue.
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Where should the human approval gate go?
Set the review point before testing, and require approval for writes to shared or authoritative design data, overwrites, deletions, permission changes and use of agent output for consequential decisions. Approval should name the specific proposed action and artifact; do not treat a general instruction to “finish the task” as advance authorization for later changes.
The reviewer must have the authority and technical context to assess the change. As DOE GEAR puts it: “An AI system cannot own a decision or accept risk.” The agent can prepare a patch or report, but responsibility for accepting the change remains with the accountable people and organization.
How do I review AI-generated Verilog before tape-out?
Review the actual diff and its effect on the design, not just the agent’s explanation. Generated RTL, scripts, constraints, citations and tool output are unverified until checked through the project’s established process. Apply checks appropriate to the artifact and design stage; there is no single test sequence established for every chip project.
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- For RTL changes: use the project’s applicable syntax and lint checks, simulation, and formal checks where the team uses them. Check interfaces, assumptions and relevant constraints against a trusted reference or baseline.
- For later-stage changes: run the relevant synthesis, timing, physical-design or sign-off checks before acceptance. A result from an earlier stage does not establish that a later-stage requirement has been met.
- For scripts and constraints: inspect what they read, write and execute, then validate their effects in the controlled flow. Do not infer correctness from plausible comments or a successful run alone.
Require qualified review before accepting consequential changes. The ASIC-Agent and AiEDA research projects illustrate multi-step agentic EDA workflows and the need for verification and sandboxing; they are research architectures, not evidence that autonomous chip design is safe for production.
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Keep a reproducible record sufficient to reconstruct what happened: model and tool identifiers, instruction and permission-policy versions, data provenance, actions and tool calls, approvals, errors, and test and review outcomes. Protect those logs: they can expose sensitive project information. Avoid recording secrets or unrestricted design content when it is not needed for accountability.
Put limits around iterations, cost, runtime, jobs and external actions. Provide an operator with a way to stop the workflow and recover the project from a known version. Before shared or operational use, test the controls themselves, not just the agent’s design output.
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- Try to access files outside the assigned project boundary.
- Attempt an unauthorized tool invocation, shell command, network request or write from a read-only stage.
- Try to bypass the approval gate or follow hostile instructions embedded in retrieved content.
- Exceed resource limits or expose secrets through output or logs.
Repeat these tests after material changes to the model, prompts, tools, retrieval data, memory, permissions or framework. A control that worked with one configuration is not proof it still works after the workflow changes.
What do current standards and AI rules establish?
IEEE P4102 is an active project to develop guidance for AI use in hardware and software development of electronic systems and integrated circuits. Its listed scope includes privacy, intellectual property, information security, global AI regulations, compliance testing and agentic-AI workflow practices. The project page identifies it as an active PAR approved on March 26, 2026; it is work in progress, not an adopted standard.
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