Diagnose excess standby power by first making a repeatable no-load measurement, then tracing the losses through the startup network, controller switching, feedback and bias circuitry, and the switch clamp. Always record input voltage and frequency, output condition, and operating mode: a standby figure without those conditions is not a meaningful comparison. No single standby-power target applies to every flyback supply.
Define a comparable standby measurement
Before changing components, establish what “standby” means for the unit. An unloaded output is not the same as a product in standby while internal circuitry remains powered. Record the AC input voltage and frequency, output voltage, connected output load, operating mode, and real input power. Repeat at the relevant low- and high-line conditions when practical; do not estimate real power from RMS current alone.
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Line voltage can materially change the result. In Texas Instruments’ TIDA-01417 report, a 24 V flyback output condition measured 36 mW at 90 VAC, 38 mW at 120 VAC, 38 mW at 150 VAC, 40 mW at 180 VAC, 40 mW at 230 VAC, and 50 mW at 265 VAC. These are design-specific measurements, not a general expected range for other supplies. Read the TIDA-01417 design report.
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Trace the likely loss paths
1. High-voltage startup network
Inspect the schematic and startup circuitry for resistors that remain connected across the rectified input after startup. If they continuously draw current, they dissipate power even when the output load is absent. TI identifies this as a potentially important no-load loss, particularly at higher input voltage. Compare the measured line dependence with the circuit: rising standby power at high line can be consistent with startup-network loss, but it does not prove that this is the cause.
For a redesign, integrated high-voltage startup or a controller with sufficiently low startup current may allow lower startup losses. That is a design option, not a repair prescription for an unidentified converter. TI’s isolated-flyback instructional material discusses the startup and other no-load loss mechanisms.
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2. Light-load switching and gate-drive activity
Observe how the controller behaves at the defined no-load or standby condition. A fixed-frequency controller may continue switching and incur frequency-related switching and gate-drive losses. A controller that reduces frequency or enters burst or valley operation can reduce those losses; the controller’s actual behavior in the circuit matters more than its advertised mode name.
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3. Secondary feedback and bias consumption
Review the no-load current drawn by secondary-side regulation and its bias circuitry. Feedback components still consume power when little or no output power is being delivered; TI’s instructional example describes feedback-circuit dissipation in the tens of milliwatts, which can be substantial in a small standby budget.
Primary-side regulation can remove the optocoupler and secondary feedback components in a suitable design. It is a topology choice for a compatible redesign, not evidence that a particular secondary-feedback circuit is faulty.
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4. Switch capacitance and clamp or snubber loss
Switching-device output capacitance and gate charge contribute to light-load switching loss. Also examine how the clamp or snubber dissipates leakage energy. TI’s example reports that raising clamp voltage reduced temperature and improved efficiency, but also warns that the primary FET must not be overvolted. An RC clamp may cost less while being less accurate and dissipating more power at very light burst-mode loads.
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Do not change clamp components blindly. Calculate the trade-off, inspect actual switch waveforms, and verify voltage ratings and margin before making a change.
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Interpret published figures in context
Reference-design measurements help show what different circuits have achieved, but they are not pass/fail limits for an unspecified product. The following figures are tied to the particular design and test condition stated by TI:
| Design example | Published standby or no-load result | Qualification |
|---|---|---|
| TI fixed-frequency instructional example | 150 mW at 80 VAC to 750 mW at 265 VAC | TI says the example was designed around a 75 mW no-load target. The page does not state a publication year. Source |
| TI improved UCC28730 example | Below 20 mW | Specific improved example; not a guarantee for other circuits. The page does not state a publication year. Source |
| TI TIDA-01417, 24 V flyback output condition | 36 mW at 90 VAC; 38 mW at 120 VAC; 38 mW at 150 VAC; 40 mW at 180 VAC; 40 mW at 230 VAC; 50 mW at 265 VAC | Design-specific report; Texas Instruments, 2026. Source |
| TI TIDA-010058 dual-output design | 31.6 mW at 115 V/50 Hz; 54.2 mW at 230 V/50 Hz | Design-specific report; Texas Instruments, 2019. Source |
| TI PMP31248 12 V quasi-resonant reference design | Less than 6 mW at 230 VAC | Specific reference design; Texas Instruments, 2023. Source |
| TI PMP40025 48 W reference design | Less than 75 mW at 230 VAC no load | Specific reference design; Texas Instruments, 2016. Source |
The spread reflects different designs and conditions, not a universal acceptable range. Judge a unit against its own product specification and the applicable requirement for its market and defined test state.
Use the measurement to choose the next check
- Power rises as input voltage rises: compare the trend with the startup network and other input-dependent losses before concluding which path dominates.
- Power remains high at no load: establish whether switching continues at a fixed rate or changes to burst or low-frequency operation, then account for gate-drive and switch losses.
- The output is nominally unloaded but consumption remains substantial: check whether secondary feedback, bias circuits, or internal product loads are still powered.
- A proposed clamp change reduces dissipation: verify the switch waveform and maximum voltage stress; a lower loss is not acceptable if it overvolts the primary switch.
Change one suspected path at a time and repeat the measurement under the same input, output, and mode conditions. This preserves a useful before-and-after comparison without confusing a change in test state with a circuit improvement.
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