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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsThe right AI-accelerator comparison is not a leaderboard of peak FLOPs. Run the same model and workload at the same precision, batch or sequence shape, software stack, latency target, and chip count; then report delivered throughput or latency together with memory, interconnect, measured energy, availability, and the cost of useful work. A capacity figure, board-watt rating, and vendor benchmark each answer a different question.
Start with a like-for-like test definition
Write the test specification before looking at products. At minimum, record:
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- Workload: training or inference, model name and version, dataset, input and output lengths, batch size, and target quality.
- Performance target: samples per second for training, or tokens per second, requests per second, and tail latency for inference.
- Precision and sparsity: BF16, FP8, or another format; dense or structured-sparse math.
- System scale: accelerator count, host CPU and memory, local storage, intra-node links, and scale-out network.
- Software: framework, compiler, kernels, runtime, communication library, model implementation, and exact versions.
- Operating conditions: utilization, power limit, cooling environment, and whether the result is a short benchmark run or a sustained production measurement.
Without these fields, “faster” usually means only that two unlike tests were placed side by side. Training favors sustained compute and communication scaling; inference may be limited by memory capacity, memory bandwidth, batching, or a strict response-time target.
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Advertised peak
Peak throughput is a theoretical ceiling under specified arithmetic assumptions. AMD lists the Instinct MI300X at 2.61 PFLOPs of FP8 compute, or 5.22 PFLOPs with structured sparsity, on its MI300X specifications page. Google’s TPU v5p documentation lists 459 TFLOPs per chip for both BF16 and FP8 at the stated configuration; see the TPU v5p documentation. Those numbers use different products and reporting conventions, and neither is a measurement of your model.
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Benchmark performance
A benchmark result is a measured outcome for a named model, system, software stack, scale, and benchmark version. For example, NVIDIA’s MLPerf results page identifies rounds and workload details. Its summary says Training v6 submissions included GB200 NVL72 and GB300 NVL72 systems and reported up to 1.6× faster training for GB300 than GB200 at the same scale. The statement describes named MLPerf submissions, not every accelerator or every workload. The page dates some training-result retrievals to June 16, 2026 and Inference v6.1 retrievals to September 16, 2026.
Production performance
Production performance is what your service or training job delivers after warm-up, checkpointing, data loading, failures, scheduling, and realistic utilization. Measure completed samples, sequences, or tokens over a defined interval, plus p50 and p95 or p99 latency for serving. A chip that wins a short synthetic test can lose when the model spills beyond memory or when communication and input pipelines are busy.
Keep compute numbers comparable
Put precision beside every FLOPs number. FP8, BF16, FP16, and lower-precision formats have different numerical behavior and may use different hardware paths. A sparse figure can be twice a dense figure without doubling the work your model can actually perform. Record whether a vendor number is dense, structured sparse, theoretical, or measured.
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Do not convert units silently. Use one convention in your worksheet (for example, tera or peta operations per second), retain the original unit in a notes column, and document any conversion. Compare the same precision and sparsity mode first; only then discuss mixed-precision strategies that your framework supports.
| Product example | Published compute figure | Qualification |
|---|---|---|
| AMD Instinct MI300X | 2.61 PFLOPs FP8; 5.22 PFLOPs FP8 with structured sparsity | AMD product specification; peak figures with different dense/sparse assumptions |
| Google Cloud TPU v5p | 459 TFLOPs BF16; 459 TFLOPs FP8 per chip | Google documentation; per-chip figures |
This table is a specification reference, not a ranking. To establish a winner, run the same model with the same precision and quality target, or use a benchmark submission that matches those conditions.
Analyze memory as capacity and bandwidth
Capacity determines whether the workload fits
Model weights, optimizer states, activations, KV cache, framework buffers, and safety headroom all consume memory. A model can fail before it performs any useful work if these allocations exceed per-chip capacity. For a distributed job, distinguish memory on one accelerator from the aggregate total: sharding may make a large model fit, but communication and replication overhead remain.
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Bandwidth determines how quickly data can move
High-bandwidth memory can feed compute units faster, but bandwidth does not increase capacity. A workload that repeatedly streams weights or activations may be bandwidth-bound even when plenty of memory is free. Record the memory type, per-chip bandwidth, and whether a quoted total is for one chip, one server, or a whole pod.
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|---|---|---|---|
| AMD Instinct MI300X | 192 GB HBM3 | 5.3 TB/s | Server-form-factor product; AMD lists a December 6, 2023 launch date |
| NVIDIA H100 SXM | 80 GB HBM3 | 3.35 TB/s | HGX eight-GPU reference: 640 GB aggregate memory |
| NVIDIA H200 SXM | 141 GB HBM3e | 4.8 TB/s | HGX eight-GPU reference: 1.1 TB aggregate memory |
| NVIDIA B200 SXM | 180 GB HBM3e | Up to 8 TB/s | HGX eight-GPU reference: 1.44 TB aggregate memory |
| Google Cloud TPU v5p | 95 GiB HBM | 2,765 GB/s | Google lists 1,200 GB/s bidirectional inter-chip bandwidth |
The H100, H200, and B200 values come from NVIDIA’s HGX technical reference, accessed October 13, 2026. The MI300X values come from AMD’s product page, and the TPU values from Google’s documentation, accessed October 13, 2026. GB and GiB are different units; preserve the vendor’s unit instead of presenting them as identical.
Check fit before throughput
- Calculate weights at the intended precision.
- Add optimizer states and gradients for training, or KV cache and runtime buffers for inference.
- Reserve headroom for fragmentation, communication libraries, and checkpoint or serving overhead.
- Divide the requirement by usable memory per chip and test the resulting shard count in the target software.
If the model fits only through aggressive offload, include the resulting host-memory traffic and latency in the benchmark. A nominal capacity advantage is not useful if the deployment cannot sustain the required service level.
Measure power use, not just the rating
A board or module rating tells you the permitted electrical envelope, not the energy consumed per training run or per token. AMD lists 750 W peak typical board power for MI300X. NVIDIA says each B200 GPU is configurable up to 1 kW in the HGX context. These are vendor specifications with different product and system boundaries; they do not show which device uses less energy for the same work.
Define the measurement boundary
- Device: accelerator-only draw, useful for thermal and rack planning.
- Server: accelerators plus host CPUs, memory, fans, drives, and power-supply losses.
- Facility: server draw multiplied by power-usage effectiveness (PUE), where available.
For an efficiency comparison, log wall power at a known sampling interval while completing a fixed amount of useful work. Report watt-hours per training step, joules per generated token, or tokens per joule, and state whether idle, startup, data loading, and cooling are included. Also record throttling and the sustained temperature, because a short peak run can hide a lower long-run clock.
Do not derive energy efficiency by dividing advertised peak FLOPs by a board rating. That quotient mixes a theoretical numerator with a power ceiling and ignores utilization, memory traffic, communication, and software overhead. No common, independent measured energy-per-task result is established here for the listed options, so a universal efficiency winner cannot be claimed.
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Compare complete systems and interconnects
Multi-accelerator performance depends on how quickly devices exchange activations, gradients, and parameters. Record the number of accelerators, intra-node links, scale-out network, topology, and measured scaling efficiency. A two-chip result, an eight-GPU HGX server, and a TPU pod are different system units.
Google describes TPU v5p as a pod-scale platform with 8,960 chips and a largest single scheduled job of 6,144 chips (96 cubes) in its documentation. Those figures describe a topology and scheduling limit, not the performance of one chip. NVIDIA’s HGX memory totals are explicitly for eight-GPU reference systems. Keep chip, node, rack, and pod results in separate rows of your comparison sheet.
Calculate scaling efficiency
Run the same workload at one, two, four, and eight accelerators when the platform supports it. Define scaling efficiency as measured throughput at n devices divided by n times one-device throughput. Explain drops caused by synchronization, all-reduce traffic, input pipelines, or memory imbalance. A platform with lower single-chip peak can deliver more useful throughput if it scales better at your required model size.
Use cost per useful work as the denominator
Separate three financial questions:
- Purchase cost: the dated quote for accelerators, servers, networking, storage, support, installation, and financing.
- Rental cost: the provider, region, machine shape, billing unit, date, minimum commitment, and interruption terms behind an hourly rate.
- Workload cost: dollars per completed training run, per million tokens at a target latency, or per unit of accepted throughput.
Include utilization, host hardware, network and storage, software engineering, power delivery, cooling, maintenance, and the number of accelerators required to meet the target. A cheap chip that needs twice as many devices or runs at half utilization may have a higher cost per result.
Historical TPU price example
Google Cloud’s December 2023 comparison published historical list prices of $3.22 per TPU v4 chip-hour, $1.20 per TPU v5e chip-hour, and $4.20 per TPU v5p chip-hour. The comparison normalized price per chip for GPT-3 175B with sequence length 2,048. These are 2023 figures, not current rates; use a current regional price sheet or quote for procurement. The source is Google’s TPU v5p and AI Hypercomputer announcement.
| TPU generation | Published historical price | Context |
|---|---|---|
| TPU v4 | $3.22 per chip-hour | Google Cloud, December 2023 comparison; normalized for GPT-3 175B, sequence length 2,048 |
| TPU v5e | $1.20 per chip-hour | Google Cloud, December 2023 comparison; same normalization |
| TPU v5p | $4.20 per chip-hour | Google Cloud, December 2023 comparison; same normalization |
Token-cost example with unlike software stacks
NVIDIA’s H100 page cites SemiAnalysis InferenceX for an April 2026 GPT-OSS-120B example: about $0.09 per million tokens for H100 at 66 tokens per second per user using vLLM, and about $0.02 per million tokens for B200 at 55 tokens per second per user using TensorRT-LLM. The figures are presented on NVIDIA’s H100 page. Because the software stacks and throughput differ, this is not a controlled same-software head-to-head, a current purchase price, or a general total-cost-of-ownership result. Treat it as a scenario-specific citation and reproduce the conditions before using it in a decision.
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A repeatable comparison workflow
- Define the service or training objective. Write the model, quality target, throughput, latency percentile, maximum job time, and availability requirement.
- Choose the smallest representative test. Use production-like sequence lengths, batch behavior, input pipeline, and checkpoint pattern. A toy model can hide memory and communication limits.
- Freeze software. Pin framework, compiler, drivers, kernels, communication libraries, model code, and configuration. Record any vendor-tuned flags.
- Verify fit and partitioning. Measure peak memory, shard layout, host-memory use, and whether offload or recomputation is enabled.
- Run a warm-up, then a sustained interval. Exclude compilation if you want steady-state throughput, but report compilation and startup separately when they affect real jobs.
- Capture performance and reliability. Log throughput, latency percentiles, step time, scaling efficiency, errors, retries, and thermal throttling.
- Measure energy at a declared boundary. Sample wall power and calculate energy per completed unit, not just average watts.
- Price the deployed system. Apply the actual accelerator count, utilization, host and network charges, storage, operations, and facility overhead to the measured work rate.
- Run sensitivity cases. Recalculate for shorter and longer sequences, different batch sizes, peak and normal utilization, and plausible regional rates.
- Document availability and support. A theoretical choice is not deployable if the required cloud region, quota, compiler, model library, or service contract is unavailable.
How to read vendor and MLPerf claims
Use a vendor page to locate a result, then inspect the underlying benchmark record. Confirm the round, model, dataset, system name, accelerator count, software versions, precision, and result type. “Up to” language describes the best qualifying submission in a stated set; it does not predict every model.
MLPerf is useful because entries are named and contextualized, but a result from one round may not match a later round, and training and inference are separate workloads. Preserve the benchmark date and retrieval date in your notes. If your model, latency target, or scale differs materially, label the result as directional rather than substituting it for an acceptance test.
Common comparison mistakes and their fixes
Ranking peak FLOPs across precisions
Failure: treating an FP8 sparse peak as equivalent to a dense BF16 result. Fix: place precision and sparsity in the same table cell and compare measured results at a common mode.
Adding memory capacities without checking sharding
Failure: calling an eight-device aggregate capacity “per-chip memory.” Fix: keep per-chip, node, and pod totals in separate columns and include replication and communication overhead.
Calling a watt rating an efficiency result
Failure: selecting the lowest board rating as the greenest system. Fix: measure energy per completed sample, step, or token at the same quality and system boundary.
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Comparing hourly prices from different dates or regions
Failure: treating a historical list price as a current quote. Fix: attach provider, region, date, machine shape, billing terms, and utilization assumptions to every rate.
Ignoring software and availability
Failure: choosing hardware whose compiler or model path cannot deliver the required kernels. Fix: run the exact framework and model, verify quotas and regions, and include engineering work in the deployment cost.
Turn measurements into a decision
Set pass/fail gates before weighting scores. A practical order is:
- Fit gate: the model and runtime state fit with documented headroom.
- Quality gate: quantization or sparsity does not violate accuracy or convergence requirements.
- Service gate: throughput and p95 or p99 latency meet the target under sustained load.
- Reliability gate: the system completes representative jobs without unacceptable errors or thermal throttling.
- Economic gate: cost per accepted token, sample, or completed run fits the budget at realistic utilization.
- Operational gate: supply, region, support, networking, power, cooling, and software maintenance are feasible.
Only after a candidate passes those gates should you optimize secondary measures such as peak FLOPs per dollar. Keep a record of measured values and vendor specifications in separate columns. The final recommendation should state the workload, scale, software, date, and assumptions so another team can reproduce it.
What a defensible comparison report contains
A concise report can include one page of results and an appendix with raw logs. Include:
- Test command or configuration, model revision, data shape, precision, and benchmark version.
- Accelerator and host configuration, device count, topology, and software versions.
- Per-chip and aggregate memory, observed peak allocation, and bandwidth-sensitive symptoms.
- Steady-state throughput, latency percentiles, scaling efficiency, and failure rate.
- Average and peak power at the declared boundary, total energy, and energy per useful unit.
- Price source, date, region, utilization, all-in system assumptions, and cost per useful unit.
- Availability constraints, tuning effort, and unresolved risks.
This format prevents a specification sheet from being mistaken for a benchmark and prevents a benchmark from being mistaken for a purchase decision.
Quick Recap
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