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How to Choose Resistor and Capacitor Values for a CMOS Timer Circuit

Choose CMOS timer components from the desired pulse width or oscillator frequency and duty cycle, using the exact timer’s datasheet equations and limits.
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Choose resistor and capacitor values by starting with the timing behavior you need, then applying the equation for the exact CMOS timer and circuit topology. For a TLC555 one-shot, the nominal pulse width is approximately tW = 1.1RAC. For its standard astable oscillator, frequency depends on both timing resistors and the capacitor, while their ratio also determines the high/low timing split.

First decide: one-shot or oscillator?

A monostable, or one-shot, produces one output pulse after a trigger. Its key design target is the pulse width. An astable circuit repeatedly switches between high and low, so you need to specify both frequency (or period) and the desired high-versus-low interval.

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Do not use an equation for one mode to choose values for the other. Select the timer IC first and check its current datasheet for the documented circuit, equations, pin connections, supply conditions, and operating limits. “CMOS 555” describes a family, not one set of interchangeable specifications.

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Choose values for a TLC555 one-shot

In the monostable circuit documented in Texas Instruments’ TLC555 datasheet, revision K (January 2026), the output pulse duration is approximately:

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tW = 1.1 × RA × C

Here, tW is the pulse width in seconds, RA is in ohms, and C is in farads. To calculate a resistor from a target pulse width and a chosen capacitor, rearrange the relation:

RA = tW / (1.1 × C)

For example, with a 10 µF capacitor and a nominal target pulse width of 1 second, the calculation gives about 90.9 kΩ. A nearby standard resistor value can be used as a starting point; recalculate the nominal pulse width using the actual selected values. This is a design estimate, not a guarantee of measured timing.

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In the datasheet’s monostable circuit, the timing begins when TRIG falls below its trigger threshold. TI notes that comparator storage time can be as long as 1 µs when the trigger is grounded, limiting the minimum monostable pulse duration to 1 µs for that TLC555 arrangement. That limit should not be assumed for every CMOS timer or circuit.

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Choose values for a TLC555 astable oscillator

In the standard TLC555 astable connection, the capacitor charges through RA and RB, then discharges through RB alone. Texas Instruments gives these timing relations for this topology below 100 kHz:

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Quantity TLC555 relation
High interval tH = 0.693(RA + RB)C
Low interval tL = 0.693RBC
Period T = tH + tL = 0.693(RA + 2RB)C
Frequency f ≈ 1.44 / ((RA + 2RB)C)
Output waveform high fraction tH/T = 1 − RB/(RA + 2RB)
Output-driver duty cycle (datasheet label) tL/T = RB/(RA + 2RB)
Low-to-high interval ratio tL/tH = RB/(RA + RB)

The output waveform’s high fraction and the datasheet’s output-driver duty-cycle quantity are complementary, not synonymous. Keep that distinction in mind when a project specifies a duty cycle.

Solve from a target period and timing split

  1. Choose a practical capacitor value. This is a starting point; consider values you can source and implement, then use the equations to find the resistor values.
  2. Find the resistor combination for the target period. Calculate RA + 2RB = T/(0.693C), where T = 1/f.
  3. Use the desired high/low split to separate the resistors. For a target high fraction D = tH/T, the listed TLC555 relation gives RB/(RA + 2RB) = 1 − D. Combine this with the period equation to calculate each resistor.
  4. Round to available standard values and recalculate. Check the resulting frequency, high interval, and low interval against the actual design target, rather than assuming rounding leaves them unchanged.
  5. Check the selected device and circuit limits. Confirm the exact timer’s datasheet applies to the topology and operating conditions you intend to use.

The frequency equation alone does not guarantee the desired duty cycle: both RA and RB set the timing split. TI provides the TLC555CALC spreadsheet on its TLC555 product page to calculate an astable circuit from timing capacitance, on-time, and desired duty cycle; TI says it calculates resistor values to the nearest 1% value. Treat it as a calculation aid, then confirm the circuit and assumptions against the datasheet.

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Account for the real parts and assembled circuit

The equations provide nominal starting values. Actual timing also depends on component variation and implementation details. The TLC555 material cited here does not provide a complete general error budget covering every capacitor type, tolerance, temperature, leakage, and layout, so a single universal accuracy figure would be misleading.

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  • Use the actual resistor and capacitor values in the equations after choosing standard components.
  • For a design where timing accuracy matters, measure the assembled circuit rather than relying only on the nominal calculation.
  • Check the timer datasheet for the chosen supply voltage, pin configuration, and operating limits; do not infer that every CMOS timer supports the same conditions.

TI says the documented TLC555 monostable and astable timing intervals are independent of supply voltage in those arrangements. That statement concerns timing intervals in the described circuits; it is not a blanket guarantee about output levels or arbitrary timer circuits.

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Check the specific CMOS timer before choosing components

Manufacturer product pages illustrate why “CMOS 555” is not enough to establish operating limits. The figures below are product-specific published claims; confirm current conditions and the selected package in its datasheet.

Device Published supply/frequency information Other relevant information
TLC555 TI lists 2 V to 15 V single-supply operation and operation up to 2 MHz. TI describes high input impedance as supporting smaller timing capacitors than NE555 or LM555 devices. Its product page provides the TLC555CALC astable spreadsheet.
LMC555 TI lists a 1.5 V specified operating supply and a maximum frequency of 3 MHz. TI describes one-shot timing as controlled by one external resistor and capacitor, and astable frequency and duty cycle by two resistors and one capacitor.

Sources: Texas Instruments’ TLC555 product page, LMC555 product page, and the TLC555 datasheet. These specifications do not establish that one device is universally better: compare the requirements of your circuit with the exact part’s documentation.

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