The Tool Desk
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There is no universally best architecture. A sound choice is the one that meets measured system requirements with enough headroom, has a maintainable software path, and can be integrated, verified, prototyped, and supported within your schedule.
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1. Turn the product idea into measurable requirements
Start with a requirements document that can survive design reviews. Keep assumptions visible so the shortlist can be revisited when the product changes.
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Describe representative workloads
- List the real application code, operating-system services, interrupt load, peripheral traffic, cryptography, machine-learning kernels, signal-processing loops, and background tasks the processor will run.
- Specify latency targets for individual events and throughput targets for sustained work. State whether the target is average, percentile, or worst-case behavior.
- Record the expected software lifetime, update model, number of products that will share the platform, and size and experience of the development team.
Make timing and assurance requirements explicit
Say whether execution must be deterministic, whether deadlines are hard or soft, and which safety or security properties must be demonstrated. A system that occasionally misses a control deadline has a different architecture requirement from one that can queue work and retry it. Capture privilege levels, isolation, secure boot, debug lockdown, trace, fault handling, and certification obligations before selecting a core.
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Set hard budgets and headroom
Write maximum active and standby power, energy per workload, die-area and package limits, memory capacity, clock-frequency range, thermal envelope, and unit-cost target. Add performance headroom for compiler changes, feature growth, temperature, voltage, process corners, and aging. A core that barely meets a laboratory target can fail once caches, interconnect, security logic, and peripherals are included.
Do not begin with an ISA slogan such as “RISC” or “CISC.” Begin with the constraints that the finished system must satisfy.
2. Separate the ISA decision from the implementation decision
An instruction-set architecture (ISA) defines the instructions and other behavior visible to software. It also defines architectural rules such as exception handling and the memory model that operating systems and hypervisors depend on. The ISA is therefore a contract, not a performance rating.
A microarchitecture implements that contract. Pipeline depth, issue width, branch prediction, execution units, cache hierarchy, speculation, clocking, and power controls determine the implementation’s power, performance, and area. Arm describes this distinction directly: “The CPU microarchitecture determines how an implementation meets the architectural contract by defining the design of the processor and covering such things as: power, performance, area, pipeline length, and levels of cache.”
Two processors that execute the same ISA can occupy very different points on the power-performance-area (PPA) curve. Conversely, two cores with similar headline performance can differ substantially in cache behavior, real-time predictability, debug, safety features, tool quality, or integration effort. Shortlist actual processor implementations, not just ISA names, and benchmark them with your code.
3. Match the software baseline to the product
Arm profiles
Arm groups its architecture into profiles aimed at different classes of systems:
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| Profile | Intended emphasis | Typical architectural question |
|---|---|---|
| A-profile | Application processors | Can it run the required operating system, applications, virtualization, and memory-management features? |
| R-profile | Real-time systems | Can it provide the determinism, interrupt behavior, and assurance needed by deadline-driven workloads? |
| M-profile | Small, low-power microcontroller devices | Can it deliver the required control, peripheral, and sleep behavior within a tightly constrained implementation? |
The profile is a starting point, not a complete product specification. Confirm the exact architecture revision, optional features, privilege model, debug and trace capabilities, compiler support, operating-system port, and long-term maintenance plan.
RISC-V base ISA, extensions, and profiles
RISC-V starts with a base integer ISA and adds optional extensions. Its specification describes the base as a minimal set that gives compilers, assemblers, linkers, and operating systems a toolchain “skeleton” around which more customized processor ISAs can be built. Program behavior also depends on the execution environment, including the ABI and, where applicable, a supervisor binary interface.
That flexibility makes the exact software baseline a design decision. Identify the required base, extensions, privilege features, ABI, compiler versions, operating system, boot firmware, libraries, debugger, and binary-format expectations. A core that is technically RISC-V but omits an extension used by your software may require recompilation or a different software stack.
Use profiles and conformance to protect portability
A profile groups architectural features into a shared, versioned baseline. RISC-V International explains that profile-conformant cores support binary portability across implementations, while non-conforming designs may require a dedicated software stack and application recompilation. Before committing, obtain a written feature matrix from each candidate and test the intended toolchain against it.
Prefer ratified, standard features when they satisfy the product and portability matters. Treat every deviation as a software-maintenance obligation that may persist for the life of the product.
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Reduce the field in stages. First eliminate candidates that cannot meet the software, real-time, safety, security, memory, or power requirements. Next remove implementations that lack required IP, tools, debug, process support, or schedule capacity. Only then compare measured PPA and commercial terms.
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Separate non-negotiables from optimization goals
- Non-negotiable: instruction and privilege features, operating-system support, safety or security mechanisms, maximum power, memory addressability, required interfaces, and tape-out timing.
- Optimization goal: extra throughput, lower energy, smaller area, richer trace, more cache, or additional accelerator capability.
This prevents a candidate from “winning” on a secondary metric while failing a mandatory requirement.
Score evidence, not promises
For each candidate, record the test program, compiler flags, clock and voltage, cache configuration, memory latency, process assumptions, and measurement owner. Mark whether a result is measured on your workload, reproduced from an integration prototype, or supplied as an estimate. Keep ISA compliance, microarchitectural behavior, and system-level results in separate columns so they are not confused.
5. Compare implementations at system level
The processor is only one part of the chip. Use the following axes in the requirements matrix.
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Workload performance
Measure end-to-end latency and throughput on representative code, including startup, interrupts, synchronization, memory stalls, and peripheral interaction. Test realistic datasets and duty cycles. Include worst-case or bounded behavior where deadlines matter. Report headroom rather than a single peak score.
Power and energy
Measure active power, idle power, sleep entry and wake time, and energy per workload. Model clock gating, power gating, voltage changes, retention, interrupt wakeups, and the actual duty cycle. A higher-performance core can finish sooner yet still consume more energy per transaction; only the product workload can resolve that trade-off.
Area and cost
Count the core, caches, tightly coupled memories, coherency logic, interrupt and debug blocks, power-management logic, and required integration fabric. Include memory macros, physical-design overhead, test structures, packaging, and yield assumptions in the cost model. A small core that needs a larger memory system can lose its apparent area advantage.
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Memory and interconnect fit
Check bandwidth, latency, arbitration, coherency, ordering, DMA behavior, and quality-of-service requirements. Confirm that the memory subsystem can keep the target core busy without violating power or area limits. For multicore designs, define coherency domains, sharing expectations, synchronization costs, and failure behavior.
Software and tools
Verify compiler and assembler support for every instruction and extension, linker behavior, operating-system ports, libraries, profiling, sanitizers, crash dumps, trace, debugger integration, and binary compatibility. Ask how quickly security fixes and toolchain updates reach the product branch. A technically capable core can become a schedule risk if the team must maintain a private compiler fork.
Integration, security, and debug
Review interrupt routing, privilege transitions, secure boot, memory protection, isolation, cryptographic acceleration, debug authentication, trace bandwidth, error reporting, and low-power state transitions. Confirm that peripherals and interconnect IP use compatible protocols and that the verification environment can exercise reset, fault, sleep, and recovery paths.
Execution and support risk
Evaluate design-kit quality, documentation, issue-response time, reference designs, verification collateral, FPGA prototype support, foundry and process-node maturity, and the supplier’s ability to support the product for its expected lifetime. Arm’s processor-selection checklist emphasizes that processor choice must include memory, peripheral IP, debug, tools, support, process maturity, and interconnect; treat those categories as a review aid and verify the current status of each offering.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.6. Decide when specialization is justified
General-purpose core plus accelerator
An accelerator is often the cleaner choice when a narrow kernel dominates runtime but the rest of the product needs a conventional software environment. Define the command interface, data movement, buffering, interrupt behavior, coherency, driver, compiler intrinsic, and fallback path. Account for the area and power of the accelerator and its memory traffic, not only its arithmetic throughput.
Standard ISA extension
A standard extension can improve code density or execution of a known class of operations while preserving a broader software ecosystem. Confirm ratification status, toolchain support, operating-system handling, and binary portability for every target implementation.
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Custom extension or tightly coupled unit
Custom instructions can target a differentiating workload, and RISC-V explicitly allows attached coprocessors and specialized accelerators. The benefit must be demonstrated on the product workload; the available guidance does not establish a universal area or energy gain. Budget for compiler and runtime support, assembler and debugger changes, verification, documentation, portability, and long-term maintenance. Define what happens when software runs on a core without the custom feature.
Specialization is justified when workload evidence is strong, the interface is stable, and the organization can support the complete hardware-software toolchain. It is risky when the workload is still changing or when compatibility across products matters more than peak efficiency.
7. Plan a practical evaluation and prototype flow
- Freeze the workload set. Select representative applications, data sizes, interrupt patterns, and background activity. Define latency, throughput, energy, and worst-case measurements.
- Write the architectural baseline. Record the ISA or profile, extensions, privilege model, ABI, operating system, boot flow, memory model, and required peripherals.
- Request implementation data. Obtain pipeline and cache descriptions, clock and voltage assumptions, area methodology, power states, debug and trace features, process targets, and verification evidence.
- Build software early. Compile the real application and operating-system components with the intended compiler, libraries, linker, debugger, and firmware. Track unsupported instructions, ABI mismatches, driver gaps, and performance cliffs.
- Model the memory and interconnect. Use realistic latency, bandwidth, arbitration, DMA, coherency, and peripheral traffic. Do not evaluate a core with an idealized memory system that the final chip cannot provide.
- Prototype the integration when risk warrants it. An FPGA development board can expose reset, boot, interrupt, peripheral, driver, and software bring-up problems before tape-out. Check that the board has enough logic, memory, transceivers, pins, and interfaces for the processor and the rest of the SoC; capacity and interfaces must match the actual design.
- Run compliance and system tests. Use architecture compliance tests, operating-system tests, security tests, fault injection, power-state transitions, and application workloads. Arm System Architecture documentation describes requirements spanning processor features, memory, PCIe integration, interrupts, power states, and peripherals, and notes that compliance testing can be performed before tape-out.
- Correlate models with implementation. Re-measure frequency, power, area, and performance as RTL, physical constraints, memory macros, and process conditions become realistic. Record the conditions beside every result.
- Make the go/no-go decision. Choose the candidate that meets all non-negotiables with documented headroom and the lowest combined technical and execution risk. If none qualifies, change the requirements, implementation, or schedule rather than hiding the gap in an average benchmark.
8. Common failure modes and how to avoid them
Assuming the ISA determines PPA
ISA labels do not reveal pipeline, cache, memory, clock, or process choices. Compare measured implementations and include the full SoC.
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Small loops can fit in cache and omit interrupts, drivers, synchronization, and memory contention. Use application traces and report conditions.
Ignoring software friction
An unsupported extension, immature debugger, missing operating-system port, or private compiler fork can erase a hardware advantage. Compile and debug the real stack before the architecture is locked.
Over-customizing too early
Custom instructions create verification and maintenance obligations. First establish that the workload is stable and that a standard extension or accelerator cannot meet the need.
Leaving memory and peripherals until late
A fast core starved by memory or blocked by interconnect arbitration will not deliver its headline result. Model these components during the shortlist phase.
Prototyping an incomplete system
An FPGA demonstration that omits production peripherals, boot security, power states, or realistic memory traffic can provide false confidence. Prototype the integration risks that are hardest to discover in simulation.
9. A decision checklist for the architecture review
- Are the representative workloads, deadlines, throughput targets, duty cycles, and software lifetime documented?
- Are maximum power, energy, area, memory, frequency, thermal, and cost limits stated with headroom?
- Is the ISA or profile, extension set, privilege model, ABI, operating system, and toolchain fixed for evaluation?
- Have actual candidate implementations been compared rather than ISA names alone?
- Are cache, memory, interconnect, DMA, coherency, peripherals, interrupts, debug, trace, and power states included?
- Are safety, security, compliance, and update requirements testable before tape-out?
- Does every custom feature have a compiler, runtime, verification, portability, and maintenance owner?
- Can the chosen design be prototyped with sufficient FPGA capacity and interfaces?
- Are every PPA result and schedule assumption tied to conditions, methodology, and an accountable source?
10. The decision in one sentence
Choose the processor architecture whose software contract fits the product, whose concrete implementation meets measured system-level power, performance, and area targets, and whose memory, tools, integration, verification, and support risks the team can manage for the chip’s entire life.
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