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There is no defensible single winner from the public evidence. TSMC has the most fully documented combination of leading-edge logic and AI-oriented packaging, Samsung presents an integrated foundry, memory and packaging offer with a qualified 2.5D package for as many as eight HBM modules, and Intel Foundry has demonstrated internal 18A production with RibbonFET, PowerVia, Foveros and EMIB. Those are different strengths, not directly comparable rankings of yield, cost or available capacity.
For an AI-chip program, the practical choice depends on the logic process, HBM supply, package architecture, design enablement, qualification evidence, geography and contractual supply risk. Company roadmaps and capability pages show what each foundry says it can provide; they do not by themselves prove equivalent external customer volume or manufacturing performance.
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What an advanced AI chip actually requires
An AI accelerator is not just a logic wafer. Its performance and manufacturability depend on several tightly coupled layers:
- Compute dies: Matrix engines, control logic, cache and I/O are implemented in a chosen process technology.
- HBM: High-bandwidth memory stacks supply data to the compute dies. The number of stacks, interface width, power delivery and physical placement affect bandwidth and thermal design.
- Advanced packaging: A 2.5D interposer or a 3D stack connects dies with much shorter, denser links than a conventional package.
- Design enablement: Process-design kits (PDKs), intellectual-property blocks, electronic-design-automation (EDA) flows, reference designs and engineering support determine how quickly a chip can reach tape-out.
- Manufacturing and qualification: Yield, test coverage, assembly capacity, HBM availability, reliability data and a predictable supply contract determine whether a design can ship at scale.
A foundry can be attractive on one layer and difficult on another. A leading transistor architecture is of limited value if the required HBM package is not qualified for the product, while a sophisticated package does not compensate for a design flow that cannot close timing or power targets.
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Why process-node names cannot be ranked literally
Names such as 3nm, 2nm and 18A are company-specific labels. They do not represent a universal measurement of transistor density, speed, power, yield or manufacturability. Samsung’s 3nm and SF2 labels, TSMC’s 3nm, N2P and A16 labels, and Intel’s 18A label refer to different process generations, design rules, transistor structures and naming conventions.
Samsung describes SF2 as a second-generation MBCFET gate-all-around (GAA) process for mobile, high-performance computing, AI and automotive applications. Samsung also describes its 3nm process as GAA. Intel identifies RibbonFET, its gate-all-around transistor, and PowerVia backside power delivery as defining features of 18A. TSMC’s public material describes its 3nm SoIC stacking and schedules N2P and A16 production, but those labels should not be converted into a direct density or performance ranking against SF2 or 18A.
To compare processes responsibly, a customer needs the foundry’s design-rule manual, standard-cell libraries, SRAM options, available voltage ranges, reliability targets, design-enablement maturity and measured silicon from the specific product. A node name alone cannot supply those answers.
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| Foundry | Process evidence | Packaging and HBM evidence | Customer-adoption evidence |
|---|---|---|---|
| Samsung Foundry | SF2 is described as a second-generation MBCFET GAA process for mobile, HPC, AI and automotive; Samsung also describes its 3nm process as GAA. | Samsung describes a 2.5D package using a 3.3x silicon interposer with up to eight HBM modules qualified and available for production. It also describes CoW 3D packaging and hybrid copper bonding under 6 μm in development. | A July 25, 2026 memorandum of understanding with Broadcom describes prospective collaboration across memory, foundry and packaging, including packaging based on Samsung’s 2nm process. It is not proof of a completed production win. |
| TSMC | TSMC’s 2025 annual report says 3nm SoIC stacking entered volume production in 2025. The same report schedules N2P and A16 volume production for the second half of 2026. | CoWoS is described as heterogeneous integration of system-on-chip dies and HBM. TSMC also lists InFO, SoIC and COUPE in its advanced-packaging portfolio. | The cited material establishes process and packaging capability statements, but a customer’s qualification, allocation, lead time and shipped volume must be verified for each design. |
| Intel Foundry | Intel reported 18A entered production in 2025, with RibbonFET and PowerVia as core features. Its 2025 Form 10-K identifies Core Ultra Series 3 as the first product manufactured on 18A and describes 18A-P development for future Intel products and external foundry customers. | Intel describes Foveros 3D stacking and EMIB silicon-bridge packaging and positions the offer as a systems-foundry stack that includes process, IP, packaging, assembly and test. | Internal Core Ultra Series 3 production demonstrates use of 18A inside Intel. It does not by itself demonstrate broad external AI-accelerator adoption. |
Samsung Foundry: GAA logic paired with an integrated memory and package offer
Process technology and maturity
Samsung’s public process description places SF2 in the second generation of its MBCFET GAA technology. The stated application scope includes mobile, HPC, AI and automotive products. Samsung also identifies its 3nm process as GAA. These descriptions establish the transistor architecture and intended markets; they do not establish a yield percentage, wafer price or comparative performance against another company’s node.
For an AI design, the important follow-up questions are whether the desired performance libraries, SRAM variants, high-speed I/O, analog blocks and physical-design rules are released for the exact SF2 option, and whether the foundry’s qualification data covers the product’s voltage, thermal and reliability envelope. Those details are program-specific rather than implied by the SF2 name.
2.5D and 3D packaging
Samsung says its advanced heterogeneous-integration offering includes a 2.5D package with a 3.3x silicon interposer and support for up to eight HBM modules. Samsung describes those configurations as qualified and available for production. The claim is significant for large AI accelerators because HBM count and interposer area constrain bandwidth, power delivery and package routing.
Samsung also describes chip-on-wafer (CoW) for 3D packaging and development of hybrid copper bonding below 6 μm. CoW and hybrid bonding are different integration approaches: the former describes how dies are assembled during wafer-level processing, while hybrid bonding joins copper and dielectric surfaces at very fine pitch. A customer must confirm which method, die thickness, thermal path and test flow apply to its product.
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Customer access and ecosystem questions
Samsung’s integrated positioning is intended to let a customer coordinate logic, memory and packaging with one supplier relationship. That can simplify responsibility for package bring-up, but it does not remove the need to qualify every HBM device, interposer revision, substrate and assembly site. Ask for the SF2 PDK release, supported EDA versions, third-party IP list, HBM sources, package-design rules, known-good-die policy and engineering-responsibility matrix before committing to tape-out.
What the Broadcom announcement does and does not show
On July 25, 2026, Samsung announced a memorandum of understanding with Broadcom to expand collaboration across memory and foundry technologies. The announcement says the collaboration is expected to extend to advanced packaging built on Samsung’s 2nm process. That is a prospective business collaboration. It should not be described as a shipped AI accelerator, a completed qualification or proof that external volume has been secured.
Where Samsung may fit
Samsung is a logical candidate when a program values one coordinated conversation for GAA logic, memory integration and a large HBM package, particularly when the stated eight-HBM configuration matches the accelerator’s bandwidth plan. The customer still needs independent evidence of the exact product’s yield, schedule, HBM allocation and reliability; the public capability description does not provide those comparable figures.
TSMC: the broadest publicly described advanced-packaging portfolio
Logic and 3D-stacking milestones
TSMC’s 2025 annual report says 3nm SoIC stacking entered volume production in 2025. SoIC is a 3D integration technology; this statement should not be read as a claim that every 3nm logic product or every AI accelerator uses the same stack.
The report schedules N2P and A16 volume production for the second half of 2026. A schedule is a forward-looking statement, not confirmation that production occurred on time. A customer evaluating either option should request the current process-status notice, production qualification date, mask and PDK revisions, and the specific package flow that will be available when its wafers are released.
CoWoS and HBM integration
TSMC describes CoWoS as advanced packaging for heterogeneous integration of system-on-chip dies and HBM. That architecture places multiple dies and memory stacks on a package-level interconnect, allowing the wide, short connections required by modern AI accelerators.
TSMC’s advanced-packaging portfolio also includes InFO, SoIC and COUPE. These names refer to different structures and use cases; they are not interchangeable versions of one package. CoWoS may be appropriate for a large 2.5D accelerator, while SoIC addresses 3D stacking and InFO targets other integration patterns. The customer must match die size, HBM arrangement, thermal design, power delivery and test strategy to the selected platform.
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Design ecosystem and co-development
The breadth of TSMC’s listed process and packaging technologies can reduce the number of separate technology interfaces a chip team must coordinate. It does not guarantee a slot in a particular package line or an immediate HBM allocation. For a serious engagement, obtain the package-design kit, interposer and substrate rules, HBM-vendor compatibility list, thermal-model methodology, assembly-and-test handoff, and the acceptance criteria for known-good dies.
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TSMC is compelling when the program needs a documented path that combines advanced logic with mature 2.5D and 3D options, and when the team can meet TSMC’s design, capacity and qualification requirements. Its public material gives the clearest description of a broad portfolio, but it does not provide a like-for-like public ranking of yield, cost, customer capacity or lead time against Samsung or Intel.
Intel Foundry: 18A production and a systems-foundry packaging stack
18A, RibbonFET and PowerVia
Intel reported that 18A entered production in 2025. The company identifies RibbonFET and PowerVia as core features. RibbonFET is Intel’s gate-all-around transistor architecture; PowerVia is backside power delivery intended to separate power routing from front-side signal wiring. Both affect design rules, standard-cell libraries, power integrity and physical implementation, so a team must evaluate them through the 18A PDK rather than through the marketing label alone.
Intel’s 2025 Form 10-K states that Core Ultra Series 3 is the first product manufactured on 18A. That is evidence of internal product use on the node. The same filing says Intel continues development of 18A-P for future Intel products and external foundry customers. Development for external customers is a forward-looking capability statement, not evidence that a third-party AI accelerator has shipped on 18A-P.
Foveros and EMIB
Intel describes Foveros for 3D die stacking and EMIB for silicon-bridge packaging. Foveros and EMIB solve different physical problems: Foveros stacks dies vertically, while EMIB uses a bridge embedded in the package substrate to connect adjacent dies. A system can use one technique or a combination, depending on die partitioning, bandwidth, thermal limits, assembly yield and test access.
Intel calls its offer a systems foundry spanning IP, process nodes, advanced packaging, assembly and test. That integrated scope may appeal to customers that want one supplier responsible for more of the product flow. Intel’s fact-sheet comparisons of scale or capacity are company claims and should not be treated as independently measured benchmarks.
Interpreting the 1.4-billion figure
Intel Foundry’s fact sheet states that global manufacturers shipped 1.4 billion AI chips in 2024. The figure should be written as an Intel Foundry-reported statistic, not as a neutral market total. Before comparing it with another market estimate, obtain Intel’s counting definition, including which devices, shipment channels and levels of integration are included.
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Where Intel may fit
Intel is worth evaluating when a customer values 18A’s RibbonFET and PowerVia, wants Foveros or EMIB options, or prefers a systems-foundry engagement that includes assembly and test. The public evidence is strongest for Intel’s internal 18A productization; external AI-accelerator adoption remains a separate qualification question.
Packaging and HBM: similar goals, different implementations
AI packages are often compared as though 2.5D and 3D were interchangeable labels. They are not. A 2.5D design generally places compute dies and HBM on a large interposer or bridge-connected substrate. A 3D design stacks dies vertically and requires fine-pitch bonding, thermal extraction and test access through the stack. The same accelerator may use both approaches for different die groups.
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1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minute| Company | Publicly described approach | What a customer must verify |
|---|---|---|
| Samsung | 2.5D package with a 3.3x silicon interposer and up to eight HBM modules described as qualified and available for production; CoW 3D packaging; hybrid copper bonding below 6 μm in development. | Which HBM devices and interposer sizes are qualified for the product, thermal and power limits, assembly site, test coverage and whether hybrid bonding is production-ready for the required schedule. |
| TSMC | CoWoS for heterogeneous integration of SoC dies and HBM; SoIC, InFO and COUPE in the broader advanced-packaging portfolio; 3nm SoIC stacking reported in volume production in 2025. | Exact CoWoS or SoIC variant, package capacity allocation, HBM compatibility, substrate and interposer rules, thermal model and production qualification date. |
| Intel Foundry | Foveros 3D stacking and EMIB silicon-bridge packaging within a systems-foundry offering. | Die-partitioning limits, bridge or base-die availability, HBM integration path, assembly-and-test flow, thermal resistance and external-customer qualification evidence. |
Package qualification must include corner cases that are easy to overlook: warpage during reflow, underfill behavior, HBM thermal gradients, repair or spare-die strategy, known-good-die screening, electrical test time and field-reliability commitments. A package described as production-capable is not automatically available in the volume or geography a particular customer needs.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Design ecosystem and customer access
Foundry access is more than the ability to order wafers. Before selecting a partner, ask for concrete evidence in five areas:
- PDK maturity: Confirm the release used for tape-out, supported EDA tool versions, sign-off decks, extraction accuracy and the change-control policy after design freeze.
- IP coverage: Check whether high-speed SerDes, HBM controllers, PCIe or CXL interfaces, SRAM compilers, security blocks and analog components are available at the chosen process and package.
- Reference flows: Request proven flows for chiplets, interposers, 3D stacks, power integrity, thermal analysis and package-aware timing closure.
- Engineering ownership: Define who owns failures at the die-to-package boundary, including wafer sort, known-good-die criteria, assembly, final test and root-cause analysis.
- Qualification evidence: Separate a technology demonstration, a customer tape-out, a first silicon result, a reliability-qualified product and sustained volume shipment. They are different milestones.
The official material available for all three companies does not support an equal-depth independent ranking of PDK quality, EDA support or customer-service responsiveness. Those factors must be assessed through the actual program team, references permitted under confidentiality and the contract’s acceptance criteria.
Customer adoption: how to read the evidence
Customer adoption should be reported with precise status and date. A useful hierarchy is:
- Roadmap: The company says a node or package will be available.
- Partnership or memorandum: Companies announce an intended collaboration, as in Samsung’s July 25, 2026 Broadcom memorandum.
- Design engagement: A customer is working through PDK access, design or tape-out.
- First silicon: A chip has been fabricated, but reliability and volume capability may not be established.
- Qualified production: The product and process meet agreed reliability and test criteria.
- Sustained shipment: The product is shipping at the required volume and cadence.
Intel’s Core Ultra Series 3 provides an explicit internal 18A production example. Samsung’s packaging page states that its described 2.5D configurations are qualified and available for production. TSMC reports 3nm SoIC stacking in volume production in 2025. None of those statements, by themselves, proves that a particular external AI accelerator has the same status, volume or economics.
Supply, geography, cost and yield: what is not established publicly
The official materials described here do not provide comparable, like-for-like figures for wafer cost, defect density, yield, packaged cost, available AI-package capacity, customer allocation or lead time. It would therefore be misleading to declare one company cheaper, higher-yielding or more available than the others.
A procurement team should request those figures under the appropriate confidentiality agreement and define the measurement basis. Useful questions include:
- What wafer-start and package-assembly capacity is reserved for the program, and what is the expansion trigger?
- Are capacity commitments stated per month, quarter or year, and do they include HBM, interposer, substrate and test capacity?
- How are wafer yield, known-good-die yield, package yield and final-test fallout calculated?
- Which fabs and assembly sites can build the product, and what happens if one site is disrupted?
- What are the non-recurring engineering charges, mask costs, reticle limits and engineering-change fees?
- Which prices are one-time, volume-dependent, geographic or promotional, and what escalation clauses apply?
Until those questions are answered on a common basis, cost and supply should remain decision variables rather than ranking claims.
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Choose Samsung when integration and HBM scale are the priority
Samsung deserves a close look if the design benefits from coordinating GAA logic, memory and packaging through one integrated supplier, and if a package supporting up to eight HBM modules fits the bandwidth and power plan. Confirm the exact SF2 option, HBM qualification, package capacity and external-customer references before treating that fit as proven.
Choose TSMC when packaging breadth and a documented co-development path matter most
TSMC’s public description covers CoWoS, SoIC, InFO and COUPE, alongside the reported 2025 volume production milestone for 3nm SoIC stacking. That breadth is useful for teams considering several 2.5D and 3D partitions. The decision still depends on the available package variant, allocation, PDK maturity and schedule for the specific design.
Choose Intel Foundry when 18A and systems responsibility align with the product
Intel fits programs that want to evaluate RibbonFET and PowerVia, combine Foveros or EMIB with Intel’s assembly-and-test flow, or coordinate more of the product through a systems-foundry relationship. Internal 18A production is established; external AI-accelerator adoption and 18A-P readiness require direct evidence for the customer’s program.
Use a dual-source strategy when risk justifies the expense
For a strategic accelerator, a second source may reduce dependence on one process, package line or geography. The cost is substantial: a second physical-design flow, different PDK and IP, new package qualification, duplicated masks and potentially different HBM interfaces. Begin by identifying which blocks can be made portable and which package choices lock the design to one supplier.
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A practical selection procedure
- Write measurable requirements. Set targets for TOPS or FLOPS, memory bandwidth, HBM capacity, power, die area, package dimensions, thermal resistance, reliability life and annual volume.
- Define the partition. Decide which functions belong on the compute die, I/O die, cache die, base die or HBM-adjacent die. Mark the links that require 2.5D, 3D or a bridge.
- Request matched technology data. Ask each foundry for the same PDK, library, package, HBM, thermal and test information. Do not compare a roadmap slide from one company with a qualified product from another.
- Run a design-enablement checkpoint. Build a small representative block, close timing and power, and verify package-aware signal integrity before committing to full-chip tape-out.
- Audit the HBM and package chain. Confirm memory vendors, interposer or bridge supply, substrate availability, assembly sites, wafer-sort flow and final-test throughput.
- Separate milestones in the contract. Define acceptance for first silicon, reliability qualification, pilot production, volume production, yield and delivery cadence.
- Model disruption scenarios. Test the effect of a delayed node, HBM shortage, package-line outage, export restriction or fab change on launch timing and cost.
- Make the decision against evidence. Score each candidate on the requirements that matter to the product, and record which scores come from measured data, contractual commitments, customer references or company statements.
Bottom line
TSMC has the broadest publicly documented advanced-packaging portfolio and a reported 2025 volume-production milestone for 3nm SoIC stacking. Samsung combines GAA logic with an explicitly described HBM-capable 2.5D package and an integrated memory-and-foundry strategy. Intel Foundry has demonstrated internal 18A production and offers RibbonFET, PowerVia, Foveros and EMIB within a systems-foundry model.
Those facts identify different strategic fits, not a universal ranking. Select the partner that can prove the required PDK, HBM and package qualification, capacity, geography, yield and delivery commitments for your exact AI chip. Public company materials do not establish a comparable winner on cost, yield or available capacity.
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