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EUV lithography projects a tiny circuit pattern onto light-sensitive material on a silicon wafer. The scanner creates 13.5-nanometer light, reflects it from a patterned mask, and focuses a reduced image onto the wafer. That exposure defines one layer—not a finished chip. Etching, deposition, implantation and many further patterning steps build the device.
What an EUV scanner does—and what it does not do
A chip is built from complex patterns added to a silicon wafer layer by layer. In lithography, a reticle (a patterned mask) carries the design for one layer, while photosensitive resist coats the wafer. The scanner transfers the reticle’s pattern into that resist; subsequent processes use the patterned resist to guide work such as etching or implantation. EUV is used for selected intricate layers, while deep-ultraviolet (DUV) lithography continues to print others. ASML’s lithography principles and its EUV system overview describe this layer-by-layer role.
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The scanner is therefore a precision pattern-projection system within a much larger fabrication sequence. It does not make transistors or complete a chip in one pass.
How EUV lithography patterns a wafer
- Prepare the reticle and wafer. The reticle holds the circuit pattern for the layer being made; the wafer is coated with light-sensitive resist.
- Generate EUV light. A source directs tin droplets through a laser interaction zone. Laser pulses flatten and vaporize the droplets into plasma, which emits EUV light at a wavelength of 13.5 nm. ASML’s current product overview describes the process as operating up to 50,000 times per second.
- Keep the light in a vacuum. EUV is absorbed by air and most materials, so the optical path must be under high vacuum. Ordinary lenses would absorb the light too, which is why the scanner uses reflective optics rather than conventional transmissive lenses.
- Reflect and reduce the pattern. The reticle is reflective, as are the multilayer mirrors that direct light through the optical column. In conventional NXE EUV systems, the optics reduce the reticle image by a factor of four before projecting it onto the wafer. Precisely positioned optical components preserve the image as it is focused.
- Expose successive fields. The scanner positions the wafer for an exposure, then moves it so the pattern can be copied across the surface. ASML says the NXE wafer stage checks and adjusts 20,000 times per second and positions the wafer within a quarter nanometer for each exposure; these are manufacturer specifications.
- Use the pattern in later fabrication steps. The exposed resist is developed, and its pattern guides operations such as etching or implantation. The wafer then proceeds through more process steps and patterning layers, using EUV for some layers and DUV for others.
ASML’s EUV product overview is the source for the wavelength, source description, vacuum and optical-path details, and NXE image reduction. ASML’s lithography principles page describes the stage specifications and lithography’s place in chip fabrication.
#1 Best Overall
- Wafer Pattern May Vary from the Product Images. Great to be used as gift, display object, exhibition, educating demonstration, testing, decoration or your collection
- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
How EUV compares with DUV
EUV and DUV are complementary lithography technologies, not competing steps where one replaces the other across an entire chip. EUV uses 13.5 nm light; high-resolution DUV uses 193 nm light. ASML expects both to remain in use in parallel for years. The choice of technology depends on the layer and manufacturing process. ASML’s EUV overview and its lithography principles page explain the technologies’ roles.
What High-NA EUV changes
ASML’s EXE High-NA platform raises numerical aperture (NA), a measure of an optical system’s ability to capture light and resolve fine detail, from 0.33 in NXE to 0.55. The higher NA is intended to improve resolution. ASML describes EXE as supporting advanced logic and memory manufacturing, but that product positioning alone does not establish a particular customer’s production status.
Rank #2
- Wafer Pattern May Vary from the Product Images. Great to be used as gift, display object, exhibition, educating demonstration, testing, decoration or your collection
- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
The optical design also changes. ASML’s January 25, 2024 explainer says EXE uses anamorphic reduction—4x in one direction and 8x in the other—while retaining the established reticle size. Its exposure field is half the size of NXE’s, so patterning a wafer requires twice as many exposures. Faster wafer and reticle stages are intended to counter that added count. These design trade-offs make High-NA a change to both imaging and exposure strategy, not simply a sharper version of the same scanner.
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Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →Outbyte Driver Updater FREEFix the driver behind crashes, sound loss and screen glitchesFind Drivers →ASML’s 2024 explainer forecast customer R&D and expected high-volume manufacturing in 2025–2026. That was a forecast published at the time, not confirmation that the transition occurred on schedule. Its stated “8 nm resolution” for EXE is an imaging capability; it does not mean every chip feature is 8 nm wide. Node labels such as “2 nm” likewise name process generations rather than promising that every transistor feature measures two nanometers. See ASML’s lenses and mirrors explainer, January 25, 2024 High-NA explainer, and current EUV product overview.
Rank #3
- 5 x 5 inches, 0.67 ounces, 0.03 inches thick. Some wafers are marked with alignment marks.
- The pattern is produced by light diffraction, and its reflective appearance changes with the viewing angle.
- Silicon wafers are fragile—please handle with care.
- Circuit details can be examined under a microscope.
How to interpret recent EUV source figures
ASML’s current product overview describes tin-droplet laser interactions up to 50,000 times per second. Its 2025 annual-report strategy page gives a different figure for the latest commercial sources: 60,000 repetitions per second. The figures refer to different descriptions of system context, so neither should be presented as a universal rate for every EUV source.
The same strategy page reports that ASML demonstrated a 1,000-watt EUV light source in April 2025. This is a company-reported demonstration, not a claim that standard production scanners use that source. Both statements are from ASML’s EUV product overview and 2025 annual-report strategy page.
Quick Recap
Best Value
- Durable Design: Crafted from high-quality, transparent plastic for long-lasting use and easy visibility of contents.
- Single Wafer Capacity: Accommodates one 12-inch silicon wafer, providing secure storage and transportation.
- Protective Features: Raised edges and secure locking mechanism help prevent wafer damage during handling.
- Compact Size: Lightweight and portable, making it convenient for lab use or transportation.
- Versatile Application: Suitable for various industries utilizing silicon wafers, such as semiconductor manufacturing.
Rank #4
- Multiple Diameter Options: Available in multiple diameters including 1, 2, 3, 4, 5, 6 and 8 inch silicon wafers
- Durable Substrate Design: Flat and solid silicon substrate supports cutting, polishing and controlled experimental handling
- Research and Educational Applications: Commonly used in laboratories, universities, research institutes and educational environments
- Precision Polished Wafer Surface: Manufactured with smooth and stable wafer surfaces, available in SSP (Single Side Polished) and DSP (Double Side Polished) configurations for sample preparation, handling, and laboratory processing.
- Wide Laboratory Applications: Commonly used in universities, research institutions, material science laboratories, and scientific training programs for silicon material studies and experimental demonstrations.
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