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1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minuteProcessing-in-memory (PIM) brings computation into memory or places it close to memory so systems can spend less time and energy moving data to separate processors. It is not one architecture: compute-in-memory, near-memory processing, and hybrid designs put computation in different places and have different tradeoffs. Recent work is advancing PIM for AI and other data-intensive tasks, but its benefits depend on the workload, system design, and software—not just on how many operations a memory-side unit can perform.
What is processing-in-memory?
In a conventional computer, processors and memory are separate. When a processor needs data, that data must travel from memory to the processor; results may then have to travel back. For workloads that repeatedly operate on large amounts of data, moving it can consume substantial time, bandwidth, and energy.
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PIM addresses that movement by doing some computation within a memory structure or on processing logic located near memory. The aim is not necessarily to replace a CPU or GPU. A PIM system may instead handle selected operations where the data resides, while conventional processors continue to run other parts of an application.
The broader term near-data processing can also include computation near storage. PIM usually refers more specifically to computation in or near memory. The labels are useful distinctions, not a single universally applied taxonomy.
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How does processing-in-memory work?
A PIM system assigns suitable work to memory-side hardware rather than sending every input to a conventional processor. For example, a data-intensive application might perform repeated operations on values stored in memory. If the system can execute some of those operations there, it may reduce transfers between memory and the main processor. The application still needs a way to identify and dispatch that work, and the system must coordinate the results with the rest of the program.
Where the computation physically occurs is a key distinction:
| Approach | Where computation happens | What distinguishes it |
|---|---|---|
| Compute-in-memory (CIM) | Within or using the memory structure itself | Selected operations use the memory structure to compute on stored data. Research includes analog and digital approaches, including designs based on emerging and memristive devices. |
| Near-memory processing | On processing logic close to memory, such as logic associated with a memory stack or module | The processing element remains distinct from the storage cells, but its proximity to memory can reduce data travel and provide high effective bandwidth. |
| Hybrid design | Across memory-side operations and conventional processing units | Combines memory-side computation with digital processing elsewhere in the system. Some analog accelerator designs, for example, pair in-memory compute tiles with digital processing units. |
These categories do not, by themselves, establish how fast, efficient, accurate, or commercially mature a particular system is. Those properties depend on the specific hardware, software, and workload.
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How is processing-in-memory advancing?
AI hardware and model design are being co-optimized
Deep-learning acceleration is a prominent research direction. A 2024 review in Nature Reviews Electrical Engineering describes hardware-aware neural architecture search: adapting model architecture with the characteristics of in-memory hardware in mind. It can be considered alongside optimization at the chip-architecture and system levels. The direction is significant because it treats the model and its target hardware as connected design choices, rather than assuming the hardware is a fixed destination for any model.
A separate 2024 review of memristor-based AI accelerators examines crossbar arrays, peripheral circuits, architectures, hardware-software co-design, and system implementations. The breadth of that work reflects how tightly device behavior, supporting circuitry, and system architecture are linked. A review of proposed designs, however, is not evidence that every design is ready for broad commercial deployment.
Software stacks are becoming part of the architecture
A 2025 perspective on software for analog in-memory accelerators describes systems that combine analog compute tiles with digital processing units. It identifies software support and co-design as important to scaling these systems across different deep-learning models. In practice, hardware needs a software layer that can map suitable work to memory-side units, manage data and execution, and coordinate with conventional processors. Without that layer, a promising circuit may be difficult to use across real applications.
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Researchers are exploring applications beyond AI
A survey published in 2026 lists genome analysis, mRNA quantification, mass spectrometry, quantum circuit simulation, wave modeling, and secure computation among explored PIM applications, alongside AI and data-intensive computing. These examples show the range of research interest; they should not be read as evidence that PIM is already widely deployed in those fields.
Evaluation is shifting from components to whole systems
Memory-side parallelism alone does not determine application performance. A 2024 real-system study of one PIM architecture and its evaluated workloads identified collective communication as the primary limitation. That result illustrates why system-level tests matter: coordination and data exchange can constrain scaling even when many memory-side processing units are available. It applies to the architecture and workloads studied, not automatically to every PIM design.
Can processing-in-memory make AI faster or more energy efficient?
It can reduce data movement for suitable work, which is why PIM is being explored for AI acceleration. But that potential is not a guarantee that an AI application will run faster or use less energy on a given PIM system. The outcome depends on how much of the workload can run on the memory-side hardware, how data is laid out, what precision and operations the hardware supports, and the costs of communication and coordination.
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Analog designs add another consideration: their supported operations and precision, and any resulting accuracy effects, must be assessed for the specific model and implementation. A result for one model, architecture, or test setup is not a general performance claim for PIM.
To judge a claim or compare systems, look for end-to-end measurements on the same workload and examine:
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- Where computation happens and what memory technology is used.
- Which operations and numerical precision are supported, and whether an analog design affects accuracy.
- Effective memory capacity and bandwidth, including data movement and communication overhead.
- Software and runtime requirements, and how well the system integrates with the rest of the machine.
- Measured application-level latency, throughput, and energy, along with the system scale and measurement method.
- The maturity and availability of the hardware being evaluated.
Peak figures from different workloads, simulations, or system configurations are not a fair head-to-head comparison. No single general speedup or energy-saving figure is established across PIM architectures.
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What are the challenges of processing-in-memory?
Finding and expressing suitable work
Applications do not automatically know which regions would benefit from PIM. Programmers and runtimes need a way to identify suitable operations, choose the right granularity for offloading, and express them in a form the memory-side hardware can execute. Poorly chosen work may add dispatch or coordination costs without reducing enough data movement.
Integrating with operating systems and conventional memory
PIM must fit into systems that already manage address translation, memory allocation, data sharing, and execution across CPUs and other processors. Keeping data consistent when conventional processor threads and PIM kernels access shared information is also a challenge. These are system-integration concerns, not just questions of designing a faster memory device.
Managing communication and scaling
Parallel memory-side units can still depend on communication with one another or with conventional processors. Coordination may become a bottleneck as a system grows. The 2024 real-system study’s collective-communication finding makes this issue concrete for the architecture and workloads it examined, while leaving results for other systems to be measured separately.
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Balancing devices, circuits, power, and temperature
Compute-in-memory designs, especially those using emerging devices or analog operation, must be developed together with their peripheral circuits and overall architecture. Scaling is also constrained by manufacturing, power delivery, and thermal reliability. A design that works in a small or specialized setup still has to meet these demands when integrated into a larger system.
Making software portable
Hardware-specific features can help a design excel on a particular task but make it harder to carry software across different PIM systems. Abstractions and software stacks must balance portability with access to the characteristics that make a specialized architecture useful.
What should readers take away?
PIM is an architectural strategy for reducing the cost of moving data, not a single type of chip or a universal replacement for conventional processors. Its research is progressing across devices, circuits, AI co-design, software, and system evaluation. Whether it delivers a practical advantage depends on the whole workload and system—including communication, software support, accuracy where relevant, and manufacturing and thermal constraints—not simply on computation happening closer to memory.
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