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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteFor most PCB layouts, start with a square grid. It matches orthogonal board features, common component footprints, pad pitches, and established fabrication conventions. A regular hexagonal lattice offers three principal routing directions, 60 degrees apart, instead of a square grid’s two perpendicular directions. That extra geometric choice could help on a board dominated by angled connections, but no controlled PCB study establishes shorter traces, fewer vias, lower congestion, or faster routing for hexagonal grids.
The practical decision is also less binary than it sounds. Some modern routers are not restricted to orthogonal paths, and some editors can disable cursor snapping during interactive routing. Your EDA tool’s algorithm, pad locations, pitch, design rules, grid resolution, and fabrication process matter at least as much as the lattice shape.
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What a PCB routing grid actually controls
“Grid” can describe several different mechanisms, and confusing them leads to bad comparisons.
- Editor or cursor grid: the points to which your cursor, tracks, vias, and components snap while you draw.
- Router search grid: the internal set of locations and directions an autorouter explores. It can be finer, coarser, or conceptually different from the visible editor grid.
- Geometric representation: the constraints imposed on the final copper geometry. A router may search on a grid while producing segments that are not visibly locked to that grid.
Altium describes its Situs topological autorouter as not constrained to an orthogonal grid. KiCad 8.0 documentation explains that snapping to the grid can be disabled while interactively routing. Those features mean a square snap setting does not prove that every route is orthogonal, and a non-orthogonal router is not automatically a hexagonal router.
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Before changing a grid, identify which of these settings you are changing. A visible snap preference may affect only cursor movement, while an autorouter’s resolution affects search time and memory. Neither setting alone determines whether the manufactured trace will contain horizontal, vertical, diagonal, or curved geometry.
Square and hexagonal geometry compared
| Characteristic | Square lattice | Regular hexagonal lattice |
|---|---|---|
| Principal directions represented by the lattice | Two perpendicular directions (90 degrees apart) | Three directions separated by 60 degrees |
| Natural alignment | Orthogonal board edges, rectangular footprints, and conventional via arrays | Features or connection patterns with recurring 60-degree or other angled relationships |
| Typical mental model for path length | Manhattan-style movement along horizontal and vertical steps | Movement through three lattice axes; exact cost depends on the router’s implementation |
| Evidence of PCB performance advantage | No direct head-to-head result found | No direct head-to-head result found |
The direction count is a consequence of lattice geometry, not a measured PCB result. A hexagonal grid gives a router another principal axis, which may reduce the number of doglegs for a connection that naturally runs at an angle. That benefit exists only if the tool can use the lattice, the pads and obstacles are placed compatibly, and the resulting geometry satisfies width, clearance, and manufacturing rules.
Likewise, a square grid’s apparent limitation is often less severe than the diagram suggests. A router can approximate a diagonal with a sequence of orthogonal steps, use 45-degree segments outside the grid model, or perform topological searches that are not tied to orthogonal cells. The relevant question is not how many directions the drawing of a grid contains, but which directions your particular routing engine can legally and efficiently produce.
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They match component and board geometry
Most board outlines, keep-outs, connector rows, memory buses, and rectangular footprints are organized horizontally and vertically. Pads commonly arrive in standardized rows and columns, so a square placement and routing grid can put pad centers and escape channels on predictable coordinates. That predictability simplifies fan-out planning and makes routes easier to inspect.
They fit established via-grid conventions
IPC’s The Universal PCB Design Grid System discusses a square via-grid example and argues that a common grid can reduce unnecessary bends. This is historical design guidance, not a comparison proving that square routing is faster or shorter than hexagonal routing. It does explain why square coordinates are deeply embedded in many libraries, tutorials, manufacturing checks, and team conventions.
They make constraints easier to reason about
When trace widths, clearances, drills, and pad dimensions are expressed against a regular orthogonal coordinate system, designers can quickly see whether an escape channel is wide enough. A square grid also makes repeated buses and differential-pair corridors visually consistent. Those are workflow advantages; they do not guarantee better electrical or manufacturing results.
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Where a hexagonal lattice could be useful
Angled connection patterns
If a board contains many features arranged around 60-degree relationships, a hexagonal lattice supplies a principal axis closer to those connections. In theory, that can reduce the number of directional changes needed to connect obstacles or pads. The result may be a cleaner path in a particular placement, but it must be demonstrated on that placement rather than assumed from the lattice alone.
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Curved, radial, or triangular mechanical assemblies may not align naturally with rows and columns. A hexagonal coordinate system can describe such arrangements more uniformly than a square one. Whether that helps routing depends on pad locations, copper keep-outs, layer transitions, and the router’s ability to honor the chosen coordinates.
When the tool supports it natively
A hexagonal experiment is practical only if the EDA system can represent the lattice for the operation you care about. If the editor offers only square snapping and the autorouter accepts only its own search model, manually drawing a pseudo-hex pattern does not create a hexagonal routing engine. It may simply add disconnected diagonal segments or force awkward coordinate conversions.
Pad alignment and pitch are decisive
A grid is useful only when the router can reach the objects that must be connected. Check the following before choosing either lattice:
- Pad-center coordinates: determine whether pads land on usable grid points or require off-grid starts.
- Pad pitch: compare the pitch with the grid step and the available escape channels between adjacent pads.
- Footprint rotation: a rotated component can make a nominally convenient square grid awkward, while a hexagonal grid may still not match the actual pitch.
- Obstacle coordinates: vias, copper pours, keep-outs, mounting holes, and board edges must be represented at the same resolution as the route search.
Autodesk’s autorouter guidance warns that unsuitable relationships between placement and routing grids can prevent a connection between pins even when visual space appears available. The warning is product-specific, but the underlying failure mode is general: a mathematical route can exist in continuous space while no legal sequence of grid points reaches both pads.
Grid resolution: finer is not automatically better
Reducing the grid step gives a router more candidate locations. It also increases the search space. Autodesk states that routing time rises exponentially with grid resolution and recommends choosing as large a grid as possible while still accounting for pads and design rules. Its documented minimum routing grid is 0.02 mm, approximately 0.8 mil, for the specified product guidance. That figure is a tool-specific setting, not a universal PCB limit or a recommendation for every fabricator.
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Use the coarsest resolution that can represent the smallest feature you genuinely need:
- List the smallest pad, clearance, via, and track dimensions in the design.
- Choose a candidate grid that places critical pad centers and escape gaps on reachable coordinates.
- Run a short routing test and record search time, memory use, and failed connections.
- Refine the grid only if the coarse setting blocks a route that is geometrically and manufacturably valid.
An extremely fine hexagonal grid can cost more than an equally fine square grid simply because the router’s implementation may carry additional direction or neighbor states. Conversely, a topological router may not use either lattice in the same way. Measure the actual tool rather than inferring runtime from geometry.
How EDA tools alter the square-versus-hex decision
| Tool or guidance | Documented behavior | Implication for your comparison |
|---|---|---|
| Altium Situs topological autorouter | Described as not constrained to an orthogonal grid; track width and copper clearance follow applicable design rules. | Do not treat a square editor grid as proof that the autorouter or final traces are orthogonal. |
| KiCad 8.0 interactive router | Respects configured track-width and copper-clearance rules; grid snapping can be disabled while routing. | An off-grid interactive segment may be possible without changing the project’s normal snap grid. Version matters. |
| Autodesk autorouter guidance | Placement and routing grids interact with pads and rules; documented minimum routing grid is 0.02 mm (about 0.8 mil); finer resolution increases routing time exponentially. | Evaluate alignment and runtime together, and do not treat 0.02 mm as a universal manufacturing requirement. |
| EasyEDA documentation | Track width, clearance, via diameter, and drill diameter are design-rule constraints, with real-time DRC during routing. | Use DRC to find violations of configured rules, then verify that those rules match the fabricator’s capabilities. |
These examples cover different layers of behavior. A cursor-snap toggle, an autorouter search lattice, and a final-copper geometry engine are not interchangeable. Record exactly which setting you changed when testing a grid.
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Neither lattice makes an electrically or mechanically invalid trace acceptable. At minimum, configure and check:
- trace width for each net class and current requirement;
- copper clearance between tracks, pads, vias, pours, and board edges;
- via outer diameter, finished drill, and annular-ring limits;
- layer-specific restrictions, impedance requirements, and differential-pair spacing where applicable;
- clearance to solder-mask openings, mounting hardware, and keep-outs;
- the fabrication supplier’s actual minimums for the intended board process.
EasyEDA’s real-time DRC can expose violations of the rules configured in the project. It cannot prove that those rules reflect a particular manufacturer’s process. EMA Design Automation’s 2024 routing guidance makes the same practical point: manufacturability depends on setting widths, clearances, drills, and related rules for the intended board and fabrication process.
A fair test for a real board
If you want an evidence-based answer for your design, compare grids under identical conditions. Do not route one version with relaxed clearances or a different placement.
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- Freeze the input: use the same schematic, component placement, board outline, keep-outs, layer stack, net classes, and via definitions.
- Define the grid variants: document the square or hexagonal step, allowed directions, snap behavior, and whether the router is using a separate internal search grid.
- Verify pad reachability: check that every pad and escape channel is representable at the selected resolution.
- Run equivalent routing attempts: use the same routing order, automation settings, rip-up limits, and stopping criteria.
- Record route quality: measure total copper length, number of bends, vias, layer changes, unrouted nets, clearance violations, and congestion in the same regions.
- Record computational cost: capture elapsed time and peak memory for the same machine and software version.
- Inspect manufacturability: run DRC and compare every result with the fabricator’s capabilities, not only the tool’s defaults.
- Repeat on representative boards: one small test cannot establish a general advantage. Include dense fine-pitch areas, long buses, angled mechanics, and boards with substantial keep-outs if those occur in your work.
No named statistic or controlled study currently establishes a universal winner. A board-specific measurement is therefore the responsible way to claim that one approach improves length, vias, congestion, or runtime.
Choosing a grid by board type
Rectangular digital or mixed-signal board
Use a square placement and editing grid that aligns with the dominant pad pitches and board features. Let the router use its documented non-orthogonal or topological capabilities if they are available and rule-compliant. This preserves predictable placement while avoiding an artificial assumption that every finished segment must be horizontal or vertical.
Dense fine-pitch escape region
Prioritize pad reachability, clearance, and via geometry over lattice elegance. Select a resolution that represents the smallest escape channel, then test runtime. A hexagonal direction set is useful only if it creates legal channels between the actual pad rows; otherwise it adds search complexity without opening a route.
Angled or radial mechanical assembly
Prototype both coordinate systems on the real placement. Inspect the number of directional changes and the amount of off-grid conversion required. If the EDA tool cannot natively support a hexagonal search or snap model, a topological router or carefully managed off-grid routing may provide the needed freedom without pretending the project is hex-grid based.
Common mistakes and how to correct them
Mistaking more directions for better routability
Three lattice axes do not guarantee fewer vias or shorter traces. Correction: measure those outcomes on identical boards and constraints.
Changing the visible grid but not the autorouter
A cursor setting may leave the router’s internal search unchanged. Correction: document whether you changed snapping, placement, routing search, or final geometry.
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Using an ultra-fine grid to recover one difficult connection
The added search space can cause unacceptable runtime and memory use. Correction: first adjust placement, escape strategy, or local routing; refine the grid only when the feature requires it.
Ignoring pad and placement relationships
Visually open space can still be unreachable on the chosen lattice. Correction: verify pad centers, pitch, rotations, and channel widths before launching an autoroute.
Treating DRC as a fabrication guarantee
DRC checks the configured rules, not a supplier’s undocumented capabilities. Correction: obtain the fabricator’s current width, clearance, drill, and annular-ring limits and encode them in the project.
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Comparing different rule sets
A grid that appears superior under looser clearances has not won a fair test. Correction: hold all electrical, mechanical, and manufacturing constraints constant.
A practical decision checklist
- Are most pads, vias, board edges, and keep-outs orthogonal?
- Does the chosen grid place the critical pad centers and escape channels on reachable points?
- Does the EDA tool natively support the grid for the operation you intend to test?
- Is the visible snap grid different from the autorouter’s search grid?
- Can the selected resolution represent the smallest width, clearance, via, and drill that the board requires?
- Have you measured length, bends, vias, congestion, unrouted nets, runtime, and memory under identical constraints?
- Have configured rules been checked against the actual fabrication process?
Bottom line: select the tool behavior, not the diagram
A square grid is the safest starting point for conventional PCB work because it aligns with common footprints, board geometry, and established design-grid practice. A hexagonal lattice has a genuine geometric distinction—three principal directions at 60 degrees—but the available evidence does not show a general PCB routing advantage. Use it only when your placement and EDA tool can exploit those directions, then verify the result with a controlled, rule-matched comparison. In many modern workflows, the more important choice is whether the router is topological or grid-constrained and how accurately your grid represents pads, pitches, and fabrication rules.
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