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1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minuteFPGA security is not one feature you switch on. It is a stack of controls: confidentiality of the configuration image, authentication of what gets loaded, protected key storage, controlled debug access, and a safe path for updates and recovery. Each layer answers a different threat, and the details change by vendor, device family and generation. This guide explains what each layer does, which threats it does and does not cover, and what to verify for a specific part before you commit to it.
Encryption, authentication and integrity: three different guarantees
The most common mistake in FPGA security discussions is treating “a secure bitstream” as one property. There are two separate questions.
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- Confidentiality: can someone who reads the configuration image from flash, a bus or a backup learn the design? Encryption addresses this.
- Integrity and authenticity: is the image that is about to configure the device genuine and unmodified? Authentication addresses this.
An encrypted image that nothing authenticates can in principle still be replaced with something else. An authenticated image that is not encrypted is protected from tampering, but its contents are readable. Some devices combine the two. AMD’s UltraScale documentation describes AES-GCM as providing both confidentiality and authentication, and it also documents a separate RSA-based authentication option (UG570, release 1.20.1, March 2025; UG570: Bitstream Authentication). Those are statements about AMD UltraScale-family devices. They are not universal properties of every FPGA.
| Goal | Mechanism class | Threat it addresses | What it does not cover |
|---|---|---|---|
| Keep the design secret | Configuration encryption | Disclosure and cloning from a stored or transferred image | Runtime leakage, fault attacks, tampering by itself |
| Reject altered or unauthorized images | Authenticated configuration (signature or authenticated encryption) | Tampering, unauthorized configuration | Confidentiality, unless combined with encryption |
| Protect the keys | Device key storage and provisioning controls | Key extraction and poor key lifecycle | Weak processes outside the device |
| Recover safely | Update, rollback and fallback controls | Failed or malicious updates, bricked devices | Anything not enforced on the fallback path |
Why the exact device family and settings matter
A feature name on a datasheet tells you little. Key storage, provisioning, enforcement, recovery behavior, supported algorithms and configuration interfaces all vary across families and generations.
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AMD’s UltraScale material shows how much the details matter. It describes BBRAM and eFUSE as choices for storing keys, and it warns that RSA authentication can be circumvented in specified configurations unless encryption is enforced (XAPP1267, revision 1.8, May 2025). In other words, having the authentication feature is not the same as having a secure deployment. The enforcement settings decide that.
Intel publishes its own, different material for Agilex 5 in a technology brief on protecting your IP with Agilex 5 FPGAs. That brief supports only a narrow feature statement, and it is not a basis for ranking one vendor over another. Check the current primary documentation and security advisories for the exact part you plan to use.
Threat classes to model
Not every threat applies equally to every design. Start by deciding who the attacker is and what access they have: remote, supply-chain insider, someone with a lost or stolen unit, or a lab attacker with the board in hand.
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Bitstream disclosure and IP cloning
An unencrypted configuration image can reveal design logic and initialization data. Encryption is meant to protect confidentiality while the image is stored or transferred. How well it works depends on key management, which is family-specific (AMD XAPP1267).
Tampering and unauthorized configuration
Authentication and integrity checks can reject altered images. The questions that matter are whether the check is enforced in production, what the device does when it fails, and whether an alternate, fallback or legacy configuration path leaves a weaker route open. Settings that look secure on paper can be bypassed if enforcement is incomplete, as the AMD RSA caveat above shows.
Key compromise and weak key lifecycle
Encryption and authentication are only as strong as the keys behind them. Key generation, provisioning, storage, access, rotation and device replacement are part of the security design, not implementation trivia. Where keys live, such as battery-backed RAM versus one-time-programmable fuses in AMD UltraScale devices, affects both attack exposure and operational flexibility.
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Physical and implementation attacks
Power and electromagnetic side channels, fault injection, probing, and debug or test interfaces can expose or disrupt a design, depending on what the attacker can do. NIST’s Hardware Security project identifies power side-channel leakage as a research concern. Configuration encryption does not by itself stop runtime leakage or fault attacks, so state the assumed attacker access explicitly and ask for evidence, such as independent evaluation, that the claimed resistance holds at that level.
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NIST’s IR 8517, published in November 2024, catalogs 98 hardware security failure scenarios. That is the number of scenarios in the report, not a count of FPGA vulnerabilities, incidents or attacks. It is useful as a reminder that weaknesses arise across design logic, firmware, interfaces and physical implementation. It does not tell you how often FPGAs are attacked, and no FPGA-specific attack-rate figure is established here.
Supply-chain and lifecycle weaknesses
Component provenance, design and toolchain integrity, update authorization, detection and recovery all matter alongside chip-level controls. NIST’s SP 800-193 Platform Firmware Resiliency Guidelines (2018) offers a useful frame: protect against unauthorized changes, detect them, and recover rapidly and securely. It was written for platform firmware, so apply it as lifecycle context for a system that contains an FPGA rather than as an FPGA configuration recipe. NIST’s 2026 paper on hardware-enabled security for 5G platform integrity (CSWP 36B) follows the same broad hardware-rooted approach for a different platform class.
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Protect, detect, recover: applying the lifecycle frame to an FPGA product
- Protect: encrypt where design secrecy matters, authenticate every image the device will accept, store keys in the strongest option the family offers, and lock down debug and JTAG access in production.
- Detect: decide what the device and the system do when authentication fails or an image is altered. Silent failure and silent fallback are both worth avoiding.
- Recover: define a field-recovery path that is held to the same standard as the primary image. A recovery image that skips authentication becomes the easiest way in.
Questions to put to the vendor and the design team
These are questions for investigation. Vendors will not all give the same answers.
- Which exact part, stepping and configuration path are in scope, and which security functions are supported on that family?
- Does configuration use confidentiality, authentication, or both? Which mechanisms are enabled and enforced in production?
- Where are keys generated and provisioned, where are they stored, and how are they recovered or replaced?
- What happens after an authentication failure, an interrupted update, a rollback attempt or loss of a key? Is the fallback image protected to the same standard?
- How are JTAG, debug, test, partial reconfiguration and field-update paths controlled?
- Which physical attack capabilities matter for the deployment, and what testing or independent evaluation supports claims of side-channel and fault resistance?
- How are bitstreams and toolchain outputs authenticated across build, release, transport, update and field recovery?
Framework for comparing FPGA candidates
When you compare two or more real devices, do it against a defined workload and threat model, using the same axes for each.
| Axis | What to establish |
|---|---|
| Confidentiality | Whether configuration encryption is supported, and which data it covers |
| Integrity and authenticity | Which authenticated configuration options exist, how they are enforced, and what the trust anchor is |
| Key lifecycle | Generation, storage type, provisioning interface, access controls, replacement and recovery |
| Update resilience | Authorization, rollback resistance, failure handling and secure recovery path |
| Physical resistance | Documented mitigations and evidence for the power, EM, fault, probing or debug threats you care about |
| Lifecycle and provenance | Vendor support, vulnerability advisories, development-tool trust and product lifecycle |
Declare a winner only after the exact candidate parts and requirements have been checked against current primary sources. The evidence reviewed here, from AMD UltraScale documentation, one Intel Agilex 5 brief and NIST guidance, does not support a universal vendor ranking, and no hands-on testing or head-to-head comparison underlies this article.
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Frequently Asked Questions
How do you secure an FPGA bitstream?
Combine encryption for confidentiality with authentication for integrity, store keys in the strongest option your device family offers, enforce those settings in production, and protect the fallback and update paths to the same standard. The exact mechanisms depend on the device family, so follow the current configuration guide for your part.
Is bitstream encryption enough to stop tampering?
Not by itself in general. Encryption addresses confidentiality, and authentication addresses whether the image is genuine and unmodified. Some families, such as AMD UltraScale with AES-GCM, combine both in one mechanism, but you should confirm that for your specific device.
Does a secure bitstream protect against side-channel or fault attacks?
No. Configuration protection covers the stored or transferred image. Power and electromagnetic leakage, fault injection and probing are separate threats that need their own mitigations and evidence for your assumed attacker.
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