There is no universal low-power winner. FD-SOI is worth evaluating when a design can use adaptive body biasing, low-voltage operation, or tight integration of digital, analog, and RF functions. FinFET is a strong candidate when logic density and compute-intensive performance are the main constraints. The right choice is the specific foundry platform that meets your workload, power, area, IP, schedule, and manufacturing requirements—not the process label alone.
What FD-SOI and FinFET mean for a chip designer
FD-SOI means fully depleted silicon-on-insulator. In an FD-SOI process, a thin silicon layer sits above a buried insulating layer. The transistor is designed to operate with the silicon body fully depleted of mobile charge in its off state. The structure gives designers a body-bias control opportunity: changing the voltage applied to the body can tune transistor behavior. Whether a design can use that control effectively depends on the foundry process, libraries, IP, and the chip’s control circuitry.
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FinFET is a three-dimensional transistor architecture in which the gate controls a channel formed as a narrow fin. Foundries position their FinFET platforms for high logic density and demanding compute. That can matter when a design needs more logic in a given die area or must deliver substantial processing performance. It does not, by itself, establish lower power for every workload: power depends on the actual implementation and operating point.
These labels describe different transistor approaches, not interchangeable, single-spec products. A comparison must name the node and platform on each side, then account for its libraries, available IP, voltage targets, design rules, and production options. A chip-level result cannot be inferred from the architecture name alone.
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How body biasing can change the FD-SOI trade-off
FD-SOI’s distinctive design lever is body biasing. Forward body bias can be used to tune for greater performance when needed; bias choices may also be used to manage energy efficiency and operating behavior. GlobalFoundries describes forward body biasing in its FDX platform as a way to tune performance and energy efficiency dynamically. CEA-Leti likewise describes back-biasing as a means of adjusting performance and power consumption to application needs.
That flexibility is useful only when the whole design supports it. The selected foundry must support the intended bias modes, and the relevant cell libraries and IP must be characterized accordingly. The design also needs a way to select and manage bias conditions. Those choices add engineering work and may introduce implementation overhead; the available evidence does not establish a universal overhead figure or guarantee a net power saving.
For a chip that spends much of its life in a low-activity or standby state but occasionally needs a burst of performance, adaptive control may be attractive: a designer can evaluate whether the platform’s supported bias modes can match those operating states. The benefit must be checked against the actual workload, voltage, timing, and implementation. Body biasing is not an automatic “free” speed or power improvement, and the result should not be assumed to transfer from one design to another.
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In practical terms, body biasing is a platform capability to verify, not a checkbox that guarantees a particular result. Ask which bias modes the foundry supports, whether the target libraries and IP are characterized for them, and what control circuitry and design work the approach requires. If the chip has distinct operating states, evaluate those states separately: a bias strategy that helps during one part of the workload may not provide the same benefit in another. Include the overhead of implementing and validating the control scheme in the comparison rather than counting only its intended power or performance effect.
Where each process is a stronger candidate
Consider FD-SOI when power flexibility or integration is central
FD-SOI deserves evaluation for low-power, always-on, or edge designs, particularly when adaptive body biasing can address changing operating needs. It may also fit designs that combine digital logic with analog or RF circuitry, embedded memory, high-voltage I/O, or automotive features, provided those options exist in the specific platform. GlobalFoundries describes FDX as combining digital, analog, and RF integration with adaptive body biasing for always-on consumer, industrial, and automotive applications. Its platform page also identifies embedded non-volatile memory, automotive, and high-voltage options.
CEA-Leti identifies 28–22 nm FD-SOI applications in communications—including 5G and sub-6 GHz—automotive radar and lidar, microcontrollers, smart devices and IoT, embedded AI components, and space components. These examples show areas where FD-SOI is used or considered; they are not a guarantee that a particular node, feature, or foundry service is available to every customer or project.
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That range of examples is a reason to frame the decision around the complete chip, rather than assume a process is only for one market. A communications or IoT design may value low-power operation; an automotive design may need particular platform options and qualification; a mixed-signal design may care about how analog and RF functions fit alongside digital logic. In each case, the application label is only a starting point. Confirm that the chosen process offers the required features and that they are usable with the intended libraries, IP, and production plan.
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Consider FinFET when density and compute lead the requirements
FinFET is a compelling candidate when the design’s central problem is fitting substantial logic into limited area or meeting compute-intensive performance targets. GlobalFoundries positions its FinFET offering for maximum logic density, demanding high-performance processing, and mission-critical designs. That is foundry positioning, not a matched independent benchmark showing that every FinFET implementation outperforms every FD-SOI implementation.
If the design is also RF-, analog-, memory-, or I/O-intensive, check the chosen FinFET platform’s actual feature set. Do not assume that every FinFET process offers the same integration options—or that FD-SOI automatically has every feature a system needs. Platform-level specifications and qualified IP matter more than broad architectural generalizations.
Compare the platforms against the project
Start with the chip’s measurable requirements and ask both foundries about specific offerings. GlobalFoundries frames platform selection around power, performance, area, and cost; those dimensions are useful only when compared under equivalent assumptions. Include the intended operating voltage, throughput, standby behavior, die area, required interfaces, and expected production volume in the comparison.
| Decision area | Questions for an FD-SOI platform | Questions for a FinFET platform |
|---|---|---|
| Active and standby power | Can the workload benefit from the platform’s supported operating voltages, leakage characteristics, or body-bias modes? Are the relevant modes supported by the libraries and IP? | Can the selected platform meet the power target at the required throughput and voltage? Compare active and standby conditions, not just one headline number. |
| Performance and area | Can the node, libraries, and implementation meet timing and area targets for the design’s compute needs? | Does the platform’s density advantage materially improve die area, compute capacity, or integration for this workload? |
| RF, analog, memory, and I/O | Are the needed RF, mixed-signal, embedded-memory, high-voltage I/O, or always-on options offered and qualified for the design? | Confirm the specific platform’s RF, analog, embedded-memory, and I/O support; do not infer it from the FinFET label. |
| Bias control | Are adaptive, forward, or reverse bias modes supported by the foundry, libraries, and IP? What control circuitry and implementation effort are required? | Verify the actual process options rather than presuming an equivalent body-bias mechanism. |
| Design ecosystem and schedule | Are the necessary PDKs, EDA flows, qualified IP, design services, and foundry capacity available on the project’s schedule? | Ask the same questions for the candidate platform and compare qualification status, capacity, and schedule. |
| Project cost and supply | Obtain current, project-specific estimates for wafers, masks, IP, and design effort; assess manufacturing location and expected volume. | Compare the same scope, volume, and schedule assumptions. Historical node comparisons are not current quotations. |
For a fair comparison, ask each foundry or design partner to evaluate the same functional design, target throughput, voltage and power states, area goals, and production assumptions. Compare implementation results from the applicable PDK and libraries, not just process marketing summaries. Include engineering effort, IP licensing or qualification needs, manufacturing availability, and any requirements for automotive or other specialized qualification.
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Make each comparison specific enough to expose trade-offs. “Low power” should be broken into the product’s relevant active, standby, burst, and always-on conditions; “performance” should identify the throughput or timing requirement that actually matters. Likewise, an area advantage matters only if it changes die size, integration, or another project constraint. Record the node, platform, libraries, IP assumptions, voltage, workload, and production volume alongside each result so that unlike tests are not mistaken for a fair comparison.
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Ask what is included in each platform proposal. The comparison may need to account for PDK access, qualified IP, EDA flows, design services, manufacturing location, and capacity as well as the process itself. If one option needs extra integration or qualification effort, that can affect the project schedule and total cost even if a headline process metric looks favorable. The aim is not to score abstract architectures, but to establish whether the specific offering can be designed, qualified, and manufactured for the product.
What published comparisons do—and do not—show
GlobalFoundries’ 2015 launch announcement for its 22FDX platform reported a 20% smaller die and 10% fewer masks than the specified 28 nm comparison, as well as nearly 50% fewer immersion lithography layers than its stated foundry FinFET baseline. The same announcement reported greater than 70% lower power for 22FDX-ulp versus 0.9 V 28 nm HKMG, and up to 90% lower power for certain IoT and consumer applications operating at 0.4 V versus 28 nm HKMG. It also said 22FDX-ulp could provide performance equivalent to FinFET.
Those figures are dated vendor-announcement claims for particular platforms and baselines. They should not be read as a current, general FD-SOI-versus-FinFET result: the comparisons use different reference processes and application conditions, and the cited figures are not an independent matched-workload benchmark. They can help explain why 22FDX attracted interest, but they cannot tell a present-day project which process will be cheaper, smaller, faster, or lower-power.
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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchA 2019 announcement by GlobalFoundries and Dolphin Integration described adaptive body-bias IP intended to compensate dynamically for process, voltage, and temperature variation and aging on 22FDX. The announcement quoted “up to 7x” energy efficiency at supply voltage as low as 0.4 V in the context of automated body-bias adjustment for 22FDX designs. This is an attributed claim tied to that implementation context, not a general efficiency ratio between FD-SOI and FinFET or proof of current availability for a new project.
Semiconductor Engineering’s expert discussion from about 2015 included practitioner views that low supply voltage and body-bias flexibility could be valuable for cost-sensitive IoT and wearable designs. Those comments are attributed industry opinions from that period, not a current market study or controlled process comparison.
The numbers should be kept attached to both their date and their reference point. For example, the reported power reductions compare specified 22FDX implementations with 0.9 V 28 nm HKMG, while the lithography-layer figure uses a stated foundry FinFET baseline. They are not interchangeable comparisons, and none supplies a current quotation or predicts the outcome of a new design. Treat them as historical examples of vendor positioning, then ask for current PPA results under the project’s own requirements.
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Is FD-SOI cheaper than FinFET?
There is no current, universal cost answer established by the available platform comparisons. Total project cost depends on more than wafer price: masks, design effort, IP and qualification, integration needs, production volume, and supply availability all matter. A smaller die or fewer process steps in a historical comparison does not prove that a particular FD-SOI project will cost less than a particular FinFET project today.
GlobalFoundries describes FDX as designed for system-level cost efficiency through lower power, higher integration, and reduced design complexity. Treat that as the foundry’s stated design intent, not a guarantee of lower total cost for every chip. Likewise, the company’s 2015 22FDX figures are specific to the stated platform and comparison baselines; they are not present-day offers or quotations. Request current estimates for equivalent scope and production assumptions before making a cost decision.
For a useful commercial comparison, request estimates that cover the same project scope and expected volume. Ask for current wafer and mask costs, plus any material differences in IP, design effort, verification, integration, qualification, manufacturing location, and supply timing. A platform that enables higher integration or lower system power may affect system-level economics, but whether that offsets other costs is project-specific. Keep each estimate dated and make its assumptions explicit; historical public percentages cannot substitute for a quotation.
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CEA-Leti reports that 28–22 nm FD-SOI transistors are produced in volume by STMicroelectronics, Samsung, and GlobalFoundries. That establishes commercial use of FD-SOI at those node ranges, but it does not establish that a specific process option is open, qualified, or available to a given customer. Confirm the actual node, product options, PDK access, capacity, and expected schedule with the relevant foundry.
GlobalFoundries describes FDX Fusion as a future roadmap item and asks interested customers to contact the company about planned availability. A roadmap is not a production offering. Do not base a committed design schedule on a future platform without confirming its status and the terms for access.
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A practical process-selection sequence
- Write down system-level targets. Define required throughput and latency, active and standby power states, operating voltage, die-area limit, interfaces, temperature range, and expected production volume.
- Identify features that could change the process choice. Mark whether the chip needs adaptive body bias, RF or mixed-signal integration, embedded memory, high-voltage I/O, automotive features, or mission-critical processing. Separate must-haves from preferences.
- Shortlist named platforms and nodes. Compare actual foundry offerings rather than “FD-SOI” and “FinFET” in the abstract. Verify the required libraries, IP, PDKs, EDA support, manufacturing options, and qualification status for each.
- Run comparable implementation work. Ask the foundry and design team to evaluate the same workload and constraints on each viable platform. Include the power states that matter, and model any body-bias control the FD-SOI design would actually use.
- Request like-for-like cost and schedule estimates. Include masks, wafers, IP, design and verification effort, qualification, volume, and supply assumptions. Record the date and scope of each estimate so a historical claim cannot be mistaken for a current quote.
- Choose against the binding constraint. Prefer the platform whose measured implementation and availability satisfy the system’s most important requirement. If neither platform meets the target, revisit the architecture, performance or power budget, feature set, or schedule instead of treating a process label as a fix.
It can help to make the shortlist a documented decision rather than a debate over labels. For each candidate, record the platform and node, the required features and their qualification status, the design results for the same workload, and the cost and schedule assumptions. Mark unresolved questions—such as IP access or capacity—as risks to close before committing. This makes it easier to see whether the real differentiator is body-bias flexibility, density, integration, availability, or something outside the transistor architecture.
Common selection mistakes
- Treating “low power” as one number. A design can have different active, standby, burst, and always-on requirements. Compare the states the product will actually use.
- Assuming body bias always saves energy. Bias flexibility is an option to evaluate, not an automatic improvement. Check platform support, control implementation, and results for the intended workload.
- Using old vendor percentages as current benchmarks. The 2015 22FDX comparisons have explicit baselines and conditions. They do not establish a present-day generic advantage over FinFET.
- Comparing different project scopes. A process can appear cheaper if the estimate omits IP, masks, integration, engineering, qualification, or volume differences. Ask for equivalent assumptions.
- Assuming every platform has the same ecosystem. Node-level labels do not guarantee the same PDK access, IP portfolio, feature options, capacity, or schedule. Verify each item with the provider.
- Confusing a roadmap with availability. A planned platform should not be treated as ready for production until access, status, and timing are confirmed.
Bottom line: make the decision at platform level
Choose FD-SOI for evaluation when low-power behavior, adaptive body-bias control, or integration features align with the chip’s requirements and the selected platform can support them. Choose FinFET for evaluation when logic density and compute dominate and the platform meets the design’s power and system needs. Neither is automatically cheaper or lower-power in every use case. The decisive evidence is a current, like-for-like project comparison using real PDKs, libraries, IP, manufacturing options, and cost and schedule assumptions.
Frequently Asked Questions
Which is better for low power, FD-SOI or FinFET?
Neither process is universally better. FD-SOI is worth evaluating when low-power operation, adaptive body biasing, or integration of digital, analog, and RF functions fits the design. FinFET is compelling when density and compute-intensive performance lead. Compare named foundry platforms against the same workload, voltage, power states, and implementation requirements.
Is FD-SOI cheaper than FinFET?
There is no universal current cost result. Total project cost depends on wafer and mask costs, IP, design and qualification effort, integration, production volume, and supply availability. Obtain current quotations for equivalent project scopes; historical 22FDX figures do not establish today’s cost for every FD-SOI and FinFET platform.
Can body biasing make an FD-SOI chip faster or lower power?
It can give designers a way to tune performance and energy behavior dynamically, and GlobalFoundries describes forward body biasing in FDX in those terms. The result depends on the foundry’s supported modes, libraries, IP, control implementation, workload, and operating conditions. It is not an automatic improvement or a guaranteed net saving.
When should I consider FD-SOI instead of FinFET?
Consider FD-SOI when adaptive body bias, low-power or always-on behavior, or specific RF, analog, embedded-memory, high-voltage, or automotive features are important and available on the selected platform. Consider FinFET when logic density and compute-intensive performance are the binding requirements. Check actual feature support and qualified IP on both options.
Are FD-SOI processes commercially available?
CEA-Leti reports volume production of 28–22 nm FD-SOI transistors by STMicroelectronics, Samsung, and GlobalFoundries. That does not mean every option is open or available to every customer. Confirm the exact node, PDK access, features, capacity, qualification status, and schedule with the relevant foundry.
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No. GlobalFoundries’ 2015 22FDX announcement reported figures against specific 28 nm HKMG and foundry FinFET baselines, and a 2019 GF/Dolphin Integration announcement described an “up to 7x” efficiency claim in a particular 22FDX body-bias context. These are attributed, dated vendor claims, not an independent matched-workload comparison.
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