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A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11There is no evidence-based universal winner. EUV lithography and advanced packaging constrain different, sequential stages of AI-chip manufacturing, and either can limit finished-chip deliveries. Public company disclosures show rising AI-related demand and investment at both stages, but do not provide the matched capacity, yield, utilization and lead-time data needed to identify the binding constraint for a particular accelerator and production period.
What EUV lithography and advanced packaging do
EUV lithography is a wafer-fabrication patterning technology. It uses 13.5 nm light to print the smallest features in leading-edge chips. ASML describes EUV as critical to high-volume manufacturing of today’s most advanced microchips.
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Advanced packaging comes later: it integrates dies and memory into a package designed for a product’s performance and connectivity needs. TSMC describes CoWoS as an advanced 2.5D packaging technology used as a foundation for high-performance computing and AI products.
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They are not alternatives competing to perform the same job. A chip must first be fabricated as usable dies and then assembled into its package. A shortage, low yield or slow production rate at either stage can reduce the number of complete chips available to ship.
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What the disclosures show about EUV
Scanner capability is not the same as chip output
ASML describes its EXE High-NA EUV platform as using 0.55 numerical aperture optics and 13.5 nm light, with an 8 nm resolution claim. Its materials have said the platform would support high-volume manufacturing in 2025–2026. That is a company roadmap statement; it does not establish that High-NA scanners have already raised AI-chip output.
In April 2025, ASML reported demonstrating a 1,000-watt EUV light source. This is a milestone for source power, not a direct measurement of scanner throughput in a fab or the number of usable AI chips produced.
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Equipment supply and wafer yield also matter
ASML’s 2024 SEC filing says production of its lithography systems is limited by capacity at Carl Zeiss SMT, its sole supplier of specified critical optical components. This identifies an upstream constraint on scanner production, but does not show that lithography is the overall bottleneck for a given accelerator.
Wafer yield affects how many usable dies emerge from a given amount of wafer processing. TSMC’s 2024 annual report says its lithography research and development included improving wafer yield for 2 nm risk production. Access to scanners alone therefore cannot establish the output of good dies.
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What the disclosures show about advanced packaging
CoWoS is expanding alongside AI demand
TSMC says CoWoS-R has been in volume production since 2023 and positions CoWoS as a foundation for high-performance computing and AI products. Its 2025 annual report says CoWoS has seen strong growth due to surging AI demand since 2023.
The same report says CoWoS-L at 3.5-reticle size has been in production since 2024; qualification of the 5.5-reticle size was expected in 2026. An expected qualification date is not proof that qualification has since been completed.
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Capacity investment does not quantify a shortfall
TSMC’s manufacturing information says it expanded advanced-packaging capacity in Chiayi and Tainan during 2025. Its 2024 annual report lists CoWoS, InFO and SoIC among packaging and 3D-stacking technologies being developed to meet customer needs.
These statements establish demand growth, technology development and capacity expansion. They do not state line utilization, package yield, the size of any capacity shortfall, or how many AI accelerators were delayed by packaging.
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How the two stages compare
| Question | EUV lithography | Advanced packaging |
|---|---|---|
| What it does | Patterns leading-edge features on silicon wafers; ASML specifies 13.5 nm EUV light. | Integrates dies and memory into a package; TSMC describes CoWoS as a 2.5D technology for HPC and AI. |
| Reported development or expansion | ASML reported a 1,000-watt EUV light-source demonstration in April 2025; its High-NA roadmap described support for high-volume manufacturing in 2025–2026. | TSMC says CoWoS-R has been in volume production since 2023, CoWoS-L at 3.5-reticle size since 2024, and advanced-packaging capacity expanded in Chiayi and Tainan during 2025. |
| Evidence missing to determine whether it limits a named chip | Relevant scanner availability and throughput, EUV-assigned critical layers, usable wafer starts and wafer yield for the same chip and period. | Capacity and utilization for the chip’s specific package design, package yield and actual lead times for the same period. |
The reported specifications and milestones are company statements, not a matched comparison of finished-chip output. Neither side’s investment announcements or technology milestones, by themselves, establish which step limits deliveries.
What would prove which step is the bottleneck?
A meaningful comparison needs data for the same accelerator and delivery window, not general market claims about fabs or packaging. At minimum, it would compare:
- Usable wafer starts on the accelerator’s process node.
- EUV scanner availability and throughput, plus the number of critical layers patterned with EUV.
- Wafer yield and usable dies per wafer.
- Advanced-package line capacity and package yield for that accelerator’s particular integration design.
- Actual lead times, inventories and shipment volumes at both stages over the same period.
The public disclosures summarized here do not provide that matched dataset. Without it, the defensible answer is that both stages are scaling constraints, while the binding constraint depends on the product, process node, fab, package design and time period.
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1Repair Windows errors before they cause bigger problems2Scan for outdated or missing drivers - takes under a minute3Clear out junk files and repair common Windows errorsWhy wafer availability alone may not settle the question
A fab can produce wafers without producing enough good dies, and a supply of good dies does not guarantee that the required package capacity is immediately available. Conversely, evidence of packaging expansion does not prove that packaging is the limiting step: a product could instead be constrained by wafer starts, yield, scanner availability or another part of its supply chain. The production chain is only as capable as the stages needed for that specific chip, but public announcements rarely expose enough operational detail to identify the weakest stage.
What High-NA plans mean for future production
In an announcement dated September 8, 2026, ASML and TSMC described a joint initiative around larger-format EUV photomasks. TSMC said it intends to use ASML High-NA technology in high-volume manufacturing for advanced nodes starting in 2030. This is a future intention, not an achieved production capability or evidence that High-NA has changed current AI-chip supply.
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