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EUV lithography improves how circuit patterns are printed on an individual silicon die; advanced packaging improves how separately fabricated dies are connected and integrated into a finished package. They address different parts of chip manufacturing, so they are complementary—not competing—technologies. EUV works during wafer fabrication, while packaging comes later, when dies are assembled side by side or in stacks.
What does EUV lithography improve?
Extreme ultraviolet (EUV) lithography is a wafer-fabrication process. It uses light to transfer circuit patterns onto a silicon wafer, helping manufacturers form smaller, denser features within an individual die. ASML says its EUV systems use light with a wavelength of 13.5 nm, near the X-ray range; that figure describes the light, not the size of a transistor or circuit feature. ASML’s EUV systems overview explains the process.
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The result is a patterning capability for structures on the die itself. EUV does not join separately manufactured dies, and its use alone does not establish a fixed improvement in a finished chip’s speed, power consumption, or overall performance; those outcomes depend on the design and implementation.
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What High NA EUV changes
High numerical aperture (High NA) EUV is a more advanced form of EUV lithography. ASML’s 2024 comparison says its High NA systems can print transistors 1.7 times smaller and achieve 2.9 times higher transistor density than its NXE systems. Those are ASML’s technology comparison figures, not a claim that a whole chip becomes 2.9 times faster or more capable. ASML’s High NA explainer gives the stated baseline and figures.
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What does advanced packaging improve?
Advanced packaging improves the assembly and integration of dies after their circuit patterns have been fabricated. Instead of putting every function on one large monolithic die, a design can combine multiple dies or chiplets in a package. Depending on the design, they may sit alongside one another in a 2.5D arrangement or be stacked in 3D. Packaging methods support heterogeneous integration: combining dies with different functions or process technologies.
The package-level benefits are about how those dies work together—such as the density and arrangement of their interconnects, the functions that can be combined, and the space the assembled system occupies. The specific connection method and trade-offs vary by design. TSMC describes its 3DFabric portfolio as including chip-on-wafer and wafer-on-wafer stacking, while Intel describes packaging approaches including EMIB and 3D integration. TSMC’s Advanced Packaging Services and Intel Foundry’s packaging overview describe their respective offerings.
Company examples, not universal benchmarks
Intel says its Data Center GPU Max Series SoC uses EMIB 3.5D packaging and has more than 100 billion transistors, 47 active tiles, and five process nodes. These figures describe Intel’s product example; they do not establish that every advanced package has those characteristics or that packaging alone caused a particular performance result. Intel’s foundry fact sheet provides the company’s example.
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How the two technologies differ
| Question | EUV lithography | Advanced packaging |
|---|---|---|
| When does it act? | During wafer fabrication, as circuit patterns are exposed onto a wafer. | During assembly and integration, connecting fabricated dies in a package. |
| What does it improve? | Patterning resolution and the ability to form smaller, denser structures within a die. | Die-to-die integration, interconnect arrangements, and package-level system design. |
| What is being worked on? | The circuit pattern on an individual die. | Multiple dies or chiplets combined in a package. |
| Common terms | EUV, High NA EUV, lithography, patterning. | 2.5D, 3D, chiplets, die stacking, heterogeneous integration, interposer, bridge. |
| What does it not do? | It does not connect separate finished dies into one package. | It does not print transistor patterns on a wafer or make lithography unnecessary. |
Why they are complementary, not alternatives
A chiplet-based product may use lithography to form the circuits on each die, then use advanced packaging to connect those dies into a system. The two technologies therefore address separate scaling problems: EUV concerns the structures patterned within a die; packaging concerns the integration of dies and their connections in the finished assembly. A package can combine dies made with different process technologies, so not every function must be built on one monolithic die.
TSMC’s 2020 description of 3DFabric says it allows customers to integrate compute cores with heterogeneous chiplets in denser 2D, 2.5D, or 3D interconnect configurations. That is the company’s description of its platform, rather than a universal performance claim. TSMC’s 3DFabric introduction provides the explanation.
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How to compare advanced packaging designs
There is no single packaging layout that is best for every chip. A meaningful comparison needs the specific designs and use case; useful questions include:
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- Connections: What interconnect method is used, and how dense and long are the die-to-die connections?
- Integration: Which functions and process technologies can the design combine?
- Physical constraints: What package footprint, thermal limits, and manufacturing constraints apply?
- Production maturity: Is the particular approach in development, production, or volume production?
Those factors support a design-specific evaluation, but the cited company descriptions do not provide a head-to-head performance ranking across packaging options. They also do not establish that advanced packaging is always cheaper, faster, or more energy-efficient.
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