Digital logic is the discipline of building circuits that work with two-valued signals. Boolean operations (AND, OR, NOT and their relatives) combine those signals into useful functions. Gates implement the operations. Gates wired together without memory form combinational circuits, whose output depends only on the current inputs. Add storage elements such as latches and flip-flops and you get sequential circuits, whose output also depends on what happened before. Nearly everything in a processor, from adders to registers to control units, is built from those two ideas plus careful timing.
This guide follows the order most university courses use: signals and logic levels, gates and truth tables, Boolean algebra, combinational blocks, stored state, and finally the tools (HDL, simulation, FPGAs) used to design real systems.
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Bits are a physical encoding, not just a notation
A bit has two values, written 0 and 1. In hardware those values are represented by electrical conditions. In the common positive logic convention, a high (or present) voltage means 1 and a low (or absent) voltage means 0. Real circuits are built from electronic devices; the University of Texas at Austin’s educational appendix on the subject introduces MOS transistors as voltage-controlled switches and shows how CMOS circuits are assembled from them.
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Also note that “true/false” and “1/0” are interpretations. The same wire can mean “enable is active” or “the bit is set” depending on how the designer assigns meaning. Some signals are active-low, meaning the asserted state is the low voltage.
Logic gates and truth tables
A truth table lists the output for every combination of inputs. A Boolean expression says the same thing symbolically, and a gate is the hardware that implements it. For two inputs A and B:
| A | B | AND | OR | NAND | NOR | XOR | XNOR |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
NOT has a single input and simply inverts it: 0 becomes 1 and 1 becomes 0.
The three basic operations
- AND outputs 1 only when all inputs are 1.
- OR outputs 1 when at least one input is 1.
- NOT inverts its input.
Derived operations
- NAND and NOR are AND and OR followed by NOT. Each is universal: any logic function can be built using only NAND gates, or only NOR gates. This matters in CMOS design, where NAND and NOR are natural, compact structures.
- XOR outputs 1 when the inputs differ. It is the core of addition and parity checking.
- XNOR outputs 1 when the inputs match, which makes it an equality detector for single bits.
Boolean algebra and simplification
Boolean algebra lets you rewrite a function into an equivalent one. Useful identities include:
- A + 0 = A, and A · 1 = A
- A + 1 = 1, and A · 0 = 0
- A + A = A, and A · A = A
- A + A’ = 1, and A · A’ = 0
- De Morgan’s laws: (A · B)’ = A’ + B’, and (A + B)’ = A’ · B’
De Morgan’s laws are the bridge between AND/OR and NAND/NOR forms, so they are how designers convert an expression into whichever gate type is cheapest to build.
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To simplify by hand, courses typically teach algebraic manipulation and Karnaugh maps, a grid layout in which adjacent cells differ by one input, so groups of 1s reveal terms that can be merged. Both aim at a function with fewer terms and literals.
Caveat: the algebraically smallest expression is not automatically the best circuit. Real implementations are constrained by propagation delay, power, fan-in and fan-out (how many inputs a gate can have or drive), voltage levels, noise margin and cost. Treat minimization as a starting point for a design, not the end of it.
Combinational logic: outputs depend only on present inputs
A combinational circuit has no memory. Change the inputs and, after a short propagation delay, the output reflects the new inputs, regardless of history.
Worked example: building an adder
Adding two single bits A and B gives a sum bit and a carry bit. The sum is 1 when the inputs differ, and the carry is 1 when both are 1:
- Sum = A XOR B
- Carry = A AND B
This is a half adder: one XOR and one AND gate. It cannot accept a carry from a lower bit, so for multi-bit numbers you need a full adder, which adds A, B and a carry-in (Cin):
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- Sum = A XOR B XOR Cin
- Cout = (A AND B) OR (Cin AND (A XOR B))
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| Block | What it does |
|---|---|
| Multiplexer (mux) | Selects one of several data inputs to pass to the output, based on select lines |
| Decoder | Turns an n-bit code into one active line out of 2n |
| Encoder | The reverse: converts one active line into a binary code |
| Comparator | Reports whether one number is equal to, greater than or less than another |
| Adder | Adds binary numbers, as above |
| Arithmetic logic unit (ALU) | Combines arithmetic and logic operations, with the operation chosen by control inputs |
Sequential logic: adding memory
Many things cannot be done without remembering: counting, holding a result, following a protocol. Sequential circuits introduce state. Their output depends on current inputs and on stored values from earlier.
Latches
A latch is the simplest storage element. It is built by feeding gate outputs back to inputs (two cross-coupled NOR or NAND gates form an SR latch). A latch is level-sensitive: while its enable is active, its output can follow the input; when the enable is inactive, it holds its value.
Flip-flops
A flip-flop is edge-triggered. It samples its input only at a clock edge (for example, the rising edge) and holds that value until the next one. Common types are D (stores the input), T (toggles), and JK. The D flip-flop dominates modern synchronous design because its behavior is the easiest to reason about: at each clock edge, Q takes the value of D.
Registers and counters
- A register is a group of flip-flops sharing a clock, storing a multi-bit value.
- A shift register moves bits one position per clock, useful for serial-to-parallel conversion.
- A counter is a register whose next value is its current value plus one (or some other sequence), computed by combinational logic.
Finite-state machines
A finite-state machine (FSM) models behavior as a set of states and the transitions between them. In hardware, state is held in a register, and combinational logic computes the next state (and often the outputs) from the current state and inputs. Traffic-light controllers, vending machines and protocol handlers are classic FSM examples. This register-plus-combinational-logic pattern is the template for synchronous design in general, up to and including processors.
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Timing: why clocks come with rules
In a clocked design, the combinational logic between flip-flops has to settle before the next clock edge. The key constraints are:
- Propagation delay: the time for a change to travel through gates. The longest path limits how fast you can clock the circuit.
- Setup time: how long the data must be stable before the clock edge.
- Hold time: how long the data must stay stable after the edge.
Violating setup or hold can leave a flip-flop in an undefined, metastable state. So sequential design is judged on timing as well as Boolean correctness. Exact numbers come from the datasheet of the device you are using; treat introductory material as a guide to concepts, not a source of electrical specifications.
From idea to working design
Course materials from the University of Toledo (EECS 1100 Digital Logic Design, syllabus updated 2024-07-15) and Universidad Carlos III de Madrid (Digital Electronics course guide, last modified 2021-12-13) show a consistent workflow:
- Specify the behavior: inputs, outputs and, if sequential, states.
- Model it as a truth table, Boolean expressions, a schematic or a state diagram.
- Describe it in a hardware description language (HDL) such as Verilog. An HDL describes hardware structure and behavior, and is not a program that runs step by step.
- Simulate to check behavior against the specification before building anything.
- Synthesize and implement, either in a custom chip or in a programmable device such as an FPGA.
The Toledo syllabus states the course objective as: “Use a contemporary analysis/design/simulation software/hardware toolchain to prototype in hardware various digital logic circuits entailing combinational and sequential circuits.”
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No. A schematic editor or HDL simulator is enough to learn every concept above, and it is the cheaper starting point. An FPGA board adds physical I/O (switches, LEDs, displays) and exposes real implementation issues. Vendors such as Digilent present introductory FPGA boards alongside their digital-logic learning material. If you buy one, compare software support, available I/O, included tutorials and price, and check that the tool flow suits your operating system.
A sensible study order
UC3M’s course guide proposes the following unit structure, with suggested learning times (UC3M, 2021). These are that guide’s estimates for its own course, not a general measure of how long digital logic takes to learn.
| Unit | Topic | Suggested time (UC3M, 2021) |
|---|---|---|
| I | Fundamentals | 10 hours |
| II | Fundamentals and combinational circuits | 15 hours |
| III | Latches, flip-flops and synchronous sequential circuits | 20 hours |
| IV | Memories, programmable logic devices and digital systems | 15 hours |
The largest share goes to sequential circuits, which is where most newcomers struggle. If you want a full-length reference, the Toledo syllabus names Digital Design (6th edition) by M. Morris Mano and Michael D. Ciletti; check which edition suits you and your course.
Quick Recap
Checks that you have understood
- Can you write the truth table for any two-input gate from memory, and rebuild XOR from AND, OR and NOT?
- Can you explain why a full adder needs a carry-in?
- Can you say whether a given circuit is combinational or sequential by looking for feedback or clocked storage?
- Can you explain why a faster clock can break a design that works at a slower one?
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