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Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →An L2 (level 2) cache is the second level of cache memory in a processor or computer system. It sits between the small, fast L1 cache and main memory, and it holds instructions or data that the L1 cache did not have. Its size, speed, and whether it is shared between cores all depend on the specific chip design, so the term describes a position in a hierarchy rather than a fixed piece of hardware.
Where L2 sits in the memory hierarchy
A processor’s memory is arranged in levels, ordered by distance from the processor. Each level is larger and slower than the one above it, and the levels closest to the processor hold the data that is needed most often. The usual order for cache levels is:
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- L1 cache, the first and closest level, usually split into instruction and data caches in designs that document it this way.
- L2 cache, the next level, which serves requests that L1 cannot satisfy.
- Main memory (system RAM), the level the processor reaches when no cache holds the item.
“Level 2” therefore means “the second cache level after L1,” not a particular size or speed. Some designs add further levels beyond L2, and the number of levels is itself a design choice.
What happens when the processor needs data
The processor does not normally look at L2 first. It works down the hierarchy until it finds the requested item. In the Pentium 4 microarchitecture described by Intel, the sequence for a missing item follows this path:
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- The processor requests an instruction or data item and checks the level-1 cache that applies to it.
- If L1 does not hold the item, the request goes to the L2 cache.
- If L2 holds the item (a hit), it is returned without going to main memory.
- If L2 does not hold it (a miss), the system bus accesses main memory.
The benefit is that a request that misses L1 can still be served quickly if L2 has the data, which avoids the much longer trip to main memory. The cost of a miss at L2 is the trip to main memory, which is why the size and organization of L2 matter to overall performance. Intel’s documentation for that design does not give latency numbers, so the relative speed of each level should be checked in the documentation for the specific processor.
What L2 stores
The contents of an L2 cache depend on the design. Two documented examples show the range:
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- Pentium 4 (Intel, 2001): the L2 cache stores instruction bytes and data that cannot fit in the trace cache and the L1 data cache.
- XScale (Intel, 2007): the optional L2 is the next level of the memory hierarchy for the L1 instruction and L1 data caches.
In both cases, L2 backs up the caches above it. It does not replace them.
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How L2 size and sharing vary by design
The following table lists the documented L2 examples discussed in this article. Each row applies only to the named product or family. Where the cited document does not state a value, the cell says so.
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| Design (source) | Role of L2 as described | Documented L2 capacity | Sharing as described |
|---|---|---|---|
| Intel Pentium 4 microarchitecture (Intel Technology Journal, 2001) | Stores instruction bytes and data that do not fit in the trace cache and L1 data cache; misses go to main memory over the system bus | Not stated in the cited article | Not stated in the cited article |
| Third-generation XScale (Intel architecture manual, 2007) | Optional next level below the L1 instruction and data caches | 256 KB or 512 KB, as options for that documented family | Not stated in the cited section |
| AMD Versal ACAP CPM CCIX (Architecture Manual AM016, revision 1.1, released 2020-11-24) | Integrated L2 intended to reduce latency and bandwidth demands for accelerator-to-memory accesses | 1 MB, physically addressable and physically tagged, with 64-byte cache lines | Integrated and shared, as described in that manual |
| Intel 12th Gen Core hybrid architecture (developer guide) | L2 for the logical E-core processors | Not stated in the cited guide section | Shared in banks of four logical processors |
Pentium 4: an intermediate level between L1 and memory
The Pentium 4 example shows L2 working as an intermediate store. It is a clear illustration of how the hierarchy functions in one design, but it should not be read as a description of every modern CPU. Newer processors may add or rearrange cache levels, and the Pentium 4 overview does not establish how later chips are organized.
XScale: optional L2 with two documented sizes
Intel’s third-generation XScale manual, published in 2007, describes L2 as an optional level, with 256 KB and 512 KB as configurations for that documented family. These figures describe that family only. They are not the typical size of an L2 cache in general.
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AMD Versal: a 1 MB shared L2 for accelerator access
The AMD Versal ACAP CPM CCIX architecture manual, revision 1.1 (released 2020-11-24), describes an integrated shared L2 cache. Its stated purpose is to reduce latency and bandwidth demands on accesses between accelerators and memory. For this implementation, the manual specifies 1 MB of physically addressable, physically tagged cache with 64-byte cache lines. These values apply to that architecture and revision, and later revisions or other Versal devices should be checked separately.
Intel 12th Gen Core hybrid: L2 shared in groups
In Intel’s developer guide for 12th Gen Core processors with hybrid architecture, the logical E-core processor’s L2 cache is shared in banks of four logical processors. This is an example of L2 sharing that depends on processor topology. It does not mean every core in every processor has the same arrangement.
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What L2 does not guarantee
Several common assumptions about L2 caches are not supported by the documentation cited here:
- L2 is not always private to one core. In some designs it is shared, and in others the sharing is grouped, as in the Intel 12th Gen example.
- L2 is not always shared. Sharing depends on the design, and some documents describe per-core arrangements while others do not state it.
- L2 is not a fixed size. The capacities above range from 256 KB to 1 MB, and each applies to one product line only.
- L2 does not have a universal speed. None of the cited sources gives latency values that would let you say L2 is always a set number of times slower than L1 or faster than main memory.
When a figure appears in a comparison, the processor model and the document that gives the figure should be named with it.
How to check the L2 cache of a specific processor
- Identify the exact processor model or system-on-chip, including its generation or revision, because cache design often changes between generations within one brand.
- Find the vendor’s technical documentation for that model, such as an architecture manual, developer guide, or product datasheet, and note its revision and date.
- Look for the cache section and record the stated L2 capacity, whether it applies per core, per cluster, or across the chip, and which cores or agents share it.
- If you are on a Linux system, the
lscpucommand lists the cache sizes reported for each level on the running machine, which can confirm the figures for hardware you already have. - Do not transfer a figure from one model to another. A capacity or sharing arrangement stated for one processor applies only to that processor.
Documented latency figures are not included in this check, because the cited sources do not provide them for the L2 level in general. If you need speed data, use benchmarks or measurements that name the same processor and test conditions.
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