Backside power delivery is a chip architecture that routes power through the back of the silicon wafer instead of relying on the frontside wiring layers shared with signal connections. The separation can free frontside routing space and reduce voltage loss, but the size of the benefit depends on the chip design and implementation.
What a chip’s power delivery network does
A power delivery network (PDN) carries supply and reference voltages—commonly called VDD and VSS—to the active devices on a chip. In a conventional design, power and signal wiring share the frontside back-end-of-line (BEOL) interconnect stack. As power routes approach the transistors, they pass through increasingly narrow metal lines and vias, which add resistance. imec’s explanation of backside power delivery describes this conventional arrangement.
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How backside power delivery works
A backside power delivery network (BSPDN) moves the power distribution routes to the wafer’s backside, separating them from the frontside signal network. In the process flow described by imec, the wafer is thinned, backside metal layers are formed, and nano-through-silicon vias (nTSVs) connect the backside network toward buried power rails (BPRs) near the devices. The precise structures and process sequence vary by implementation; not every BSPDN uses the same combination of rails and vias. imec’s report on enabling building blocks discusses these integration steps.
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What changes compared with frontside power delivery?
| Aspect | Conventional frontside delivery | Backside power delivery |
|---|---|---|
| Location of power routes | In the frontside BEOL stack, alongside signal interconnects. | On the backside of the silicon wafer, connected toward the devices. |
| Frontside routing | Power and signals share routing resources. | Power routing is separated from frontside signal routing, potentially freeing frontside resources for signals. |
| Connection structures | Power reaches devices through the frontside interconnect stack. | Implementations may use backside metal and structures such as nTSVs and BPRs; the details are design-dependent. |
Why chip designers use it
More room for signal routing
Removing power routes from the frontside BEOL can ease routing congestion and leave more of that wiring space available for signals. This is an architectural goal, not a guarantee that every design will achieve a particular density or performance improvement.
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Potentially lower IR drop
IR drop is the voltage lost as current passes through resistance in the power network. Backside power lines can be wider and less resistive than fine frontside routes, which can reduce that loss. The benefit depends on the implementation and design conditions.
What the cited IR-drop figures mean
imec reported an imec–Arm simulation presented at IEDM 2019 that compared buried power rails with frontside delivery against traditional frontside delivery: the simulated dynamic IR drop was about 1.7 times lower. In the same simulation comparison, buried power rails with backside delivery had a sevenfold reduction in dynamic IR drop versus traditional frontside delivery. These are results from that specific simulation, not universal measurements of shipping chips or guaranteed gains for other designs. imec’s account of the comparison provides the figures and context.
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PowerVia is one implementation, not the generic name
PowerVia is Intel’s branded backside power delivery implementation. Intel describes it as moving power routing to the backside to separate it from frontside signal routing; the term should not be used as a synonym for every BSPDN architecture. Intel’s PowerVia overview describes its approach.
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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallIn a June 2023 report about a product-like test-chip implementation, Intel said the structure required thermal mitigation and new design-debug techniques. Those are reported considerations for that implementation, not evidence that every backside power design has the same challenges. Intel’s June 5, 2023 test-chip report gives that account.
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Why buried power rails are often discussed with backside delivery
A buried power rail is a local power rail placed deep in the chip’s front-end-of-line, near the devices. It can form part of a backside delivery architecture, but buried rails and backside delivery are distinct design choices: a buried rail can be paired with different routing arrangements. imec’s Naoto Horiguchi, director of CMOS Device Technology, described combining backside delivery with buried power rails as the most promising scheme in terms of scalability and performance. That is his assessment of the approach, not a claim that all designs must use it. imec’s report on backside delivery with buried power rails includes his statement.
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