AMD MI300X Matrix Cores: What They Execute—and What MCP Means

AMD’s MI300X Matrix Cores accelerate matrix fused multiply-add (MFMA) instructions: they multiply matrix fragments and accumulate the results into output fragments. “MCP” in AMD’s partitioning documentation means Modular Chiplet Platform; it describes how GPU compute and memory resources are exposed as logical devices, not an operation performed by Matrix Cores. [AMD’s compute-partitioning documentation]

What do the MI300X Matrix Cores actually execute, and what does MCP have to do with them?

These are two different layers of the system. Matrix Cores are hardware for accelerating MFMA arithmetic. MCP is AMD’s term for a resource-organization platform used in compute partitioning. In AMD’s description, partitioning divides GPU compute and memory resources into smaller logical units that applications can address as independent devices; CPX exposes each XCD as an individual logical GPU. A partition changes what resources software sees as a device. It does not turn partitioning into matrix arithmetic.

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The acronym MCP has unrelated meanings in other computing contexts. Here it refers specifically to AMD’s Modular Chiplet Platform as used in AMD’s compute-partitioning documentation.

What an MFMA instruction does

AMD describes Matrix Cores as special-purpose hardware for matrix fused multiply-add operations, written D := A*B + C. The instruction multiplies input matrix fragments A and B, then adds the result to C to produce output fragment D. It is a defined piece of arithmetic on fragments—not a command to run an entire neural network, application, or arbitrary full matrix on its own. [AMD ROCm, “Matrix Core Programming on AMD CDNA™3 and CDNA™4 architecture,” September 30, 2025]

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AMD’s MI300 Instruction Set Architecture reference describes the core operation inside a Matrix Core as a 4 × 1 by 1 × 4 outer matrix product, yielding 16 output values. Combinations of these operations, used in parallel and in series, implement dense MFMA instructions and supported 2:4 sparse variants. That description is about the underlying fragment operation; it does not mean a single core autonomously processes a whole application. [AMD Instinct MI300 Instruction Set Architecture Reference Guide, Chapter 7]

How software issues Matrix Core work

MFMA instructions operate across a wavefront: work-items collectively execute an instruction, with each work-item holding part of the distributed A, B, C, and D operands. AMD’s CDNA examples use a 64-work-item wavefront, and the instruction set defines the layout of the operands for each instruction. In HIP, compiler-provided LLVM intrinsics let kernels issue the relevant MFMA instructions; the intrinsic specifies an instruction’s matrix shape and input/output types. Each instruction handles its prescribed tile or fragment, not a matrix of arbitrary size. [AMD ROCm Matrix Core programming article]

Results are not necessarily ready immediately after an MFMA instruction. AMD’s ISA description cautions that matrix instructions do not produce all output in one cycle and that partially written results can be observable. Code may need independent instructions between producing a result and consuming it or changing its input registers. This is a dependency and scheduling concern, not a claim that every MFMA has a fixed one-cycle latency. [AMD Instinct MI300 Instruction Set Architecture Reference Guide]

MI300X specifications: core count and peak arithmetic rates

AMD’s 2026 MI300X product specifications list 1,216 Matrix Cores and 304 compute units. The same manufacturer specifications describe a CDNA 3 accelerator in OAM server-module form, with 192 GB of HBM3, 5.3 TB/s peak memory bandwidth, 750 W peak typical board power, and a 2,100 MHz peak engine clock. These are vendor specifications, not measurements of application performance. [AMD Instinct MI300X product page]

Peak ratings describe theoretical vendor-labeled capability for the stated precision and, where specified, sparsity condition. They are not a promise that a model or kernel will sustain those rates. [AMD Instinct MI300X product page]

Precision, accumulation, and structured sparsity

MFMA instruction forms define operand and output types. AMD describes a common mixed-precision approach in which lower-precision input matrices are accumulated into FP32 outputs. Using a wider accumulator is intended to reduce accumulation error relative to also accumulating in low precision, but it is not a blanket accuracy guarantee: the result depends on the input data, formats, algorithm, and conversion choices. [AMD ROCm Matrix Core programming article]

MI300X supports documented dense and 2:4 structured-sparse MFMA instruction families. The structured-sparsity peak figures apply when the relevant sparsity format and instruction assumptions are met; they should not be read as the rate for dense work or for any arbitrary sparse matrix. The CDNA4-specific FP6, FP4, and block-scaled MFMA additions described in AMD’s broader article do not apply to this CDNA3 MI300X. [AMD ROCm Matrix Core programming article] [AMD Instinct MI300 Instruction Set Architecture Reference Guide]

Why real kernels may fall short of peak

Matrix Core throughput depends on the whole kernel around the arithmetic. The chosen instruction shape, input and accumulator types, operand reuse, movement of data, layout conversions, workgroup parallelism, occupancy, register pressure, and local data-share (LDS) use all affect how effectively a workload maps to the hardware.

AMD’s ROCm 6.2.4 MI300X tuning guidance recommends balancing GEMM tile sizes—BLOCK_M, BLOCK_N, and BLOCK_K—against data reuse, memory traffic, and workgroup parallelism. In the GEMM-kernel context covered by that guide, AMD says mfma_16x16 typically outperforms mfma_32x32, even for large GEMM and tile sizes. This is versioned tuning guidance for that context, not a universal benchmark result; layout conversion and LDS use can also affect stores and occupancy. [AMD ROCm 6.2.4 MI300X GEMM tuning guide]

What Matrix Cores do—and what they do not do

• They do: accelerate supported MFMA fragment multiplication and accumulation, using instruction forms and operand types available on CDNA 3.
• They can: execute documented dense and 2:4 structured-sparse instruction families when software supplies compatible operands and layouts.
• They do not: run a whole model or application independently, choose the application’s schedule, or implement MCP resource partitioning.
• They do not guarantee: that a workload will reach AMD’s peak ratings; software mapping, data movement, instruction dependencies, precision, and kernel resource use matter.

Host/runtime code, compilers, and kernels organize data and issue instructions. MCP partitioning determines how compute and memory resources are presented as logical devices; Matrix Cores perform the fragment-level arithmetic those kernels request.

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