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AES Instruction Set: What AES-NI Does and How Its Six Instructions Work

AES-NI is a processor instruction extension that accelerates AES operations in hardware. See what its six instructions do and what CPU support means.
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The AES instruction set is a collection of processor instructions that accelerates parts of the Advanced Encryption Standard (AES) in hardware. Intel calls its implementation AES-NI. It is not a different cipher or an encryption mode: compatible software must use the instructions to benefit, and actual speed gains depend on the processor, implementation, and workload.

What AES-NI means

AES is a symmetric-key encryption algorithm. AES-NI is Intel’s name for processor instructions that carry out computationally intensive AES operations, including encryption and decryption rounds and assistance with generating round keys. Intel describes AES-NI as a set of SIMD instructions for AES encryption and decryption. Intel’s AES-NI overview and its processor documentation explain the extension and its role.

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The distinction matters: AES defines the cipher, while AES-NI is a hardware facility that software can use to implement it more efficiently. AES-NI is not itself a cipher, mode of operation, or a feature that encrypts files automatically.

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What the six AES-NI instructions do

Intel documents six AES-NI instructions. Four handle encryption or decryption rounds; one performs an inverse transformation used in decryption; and one assists with key expansion. Intel’s instruction overview describes their roles.

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Instruction Role
AESENC Performs a non-final AES encryption round.
AESENCLAST Performs the final AES encryption round.
AESDEC Performs a non-final AES decryption round.
AESDECLAST Performs the final AES decryption round.
AESIMC Performs the inverse mix-column transformation used in the equivalent inverse cipher.
AESKEYGENASSIST Assists with generating round keys from the cipher key.

The names reflect their purpose: ENC and DEC refer to encryption and decryption, while LAST marks the final round. AESKEYGENASSIST supports key-schedule work; it does not replace the cipher key or generate a complete encryption process on its own.

How AES rounds relate to the instructions

AES operates on 128-bit data blocks. Its standard key lengths are 128, 192, and 256 bits, which use 10, 12, and 14 rounds respectively. Intel’s Software Developer’s Manual documents these block, key, and round sizes along with the instruction behavior.

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The round instructions operate on AES data as the cipher progresses. Encryption uses the non-final round instruction for intermediate rounds and the final-round instruction at the end; decryption has corresponding non-final and final instructions. Key expansion prepares round keys used during the cipher, and the inverse mix-column operation supports the equivalent inverse decryption process.

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What AES-NI support does—and does not—tell you

A processor must support AES-NI, and the software performing encryption or decryption must use the instructions, either directly or through a library or compiler implementation. Their presence alone does not make every application faster or automatically secure. Performance depends on how much of a workload is spent in AES operations, as well as the processor and software implementation. Intel’s older overview discusses workload-dependent acceleration, not a guaranteed speedup for every system.

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AES-NI support is processor-specific. Intel’s 12th Generation Core processor datasheet says the capability may not be available on every SKU. Check the exact processor model’s specifications rather than assuming all processors in a generation or product family include it. Intel’s 12th Generation Core datasheet states this qualification for that processor family.

“AES-NI” is Intel’s terminology. The cited Intel documentation does not establish a vendor-by-vendor comparison or cover naming across other processor makers, so the term should not be treated as proof that Intel is the only source of hardware AES acceleration.

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