“Chip feature size” is a physical dimension of a structure on a semiconductor chip—but it does not name one universal measurement. It may mean a transistor’s gate length, the width of a patterned feature, or the pitch or half-pitch of repeated wiring. Modern process-node labels such as “5 nm” are generation names, not reliable measurements of any one feature.
What can “feature size” measure?
The phrase is ambiguous unless the specific structure and dimension are named. Three common meanings are:
- Gate length: the physical length of a transistor’s gate, a dimension relevant to transistor behavior and logic performance.
- Critical dimension: the width or another specified dimension of a patterned feature.
- Interconnect pitch or half-pitch: the spacing between repeated metal wiring features, or half that spacing. Pitch describes a repeating pattern, not the width of one individual line.
These are different geometries. A claim that a chip has a particular “feature size” is incomplete unless it identifies which one is meant.
Why process-node names once suggested a dimension
Historically, node naming was associated with half the dimension of the smallest pitch typically used by an integrated circuit’s densest metal layer. In the 1970s, 1980s and much of the 1990s, transistor gate length and the tightest metal half-pitch were essentially the same, so one number could serve as a rough guide to both density-related scaling and performance-related transistor dimensions. The 2022 IEEE International Roadmap for Devices and Systems (IRDS) Executive Summary describes that historical convention.
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Different physical measures have long served different purposes. The International Technology Roadmap for Semiconductors (ITRS) used minimum Metal 1 half-pitch as a representative scaling measure for high-density circuits and physical bottom gate length as a representative measure for leading-edge logic performance. That distinction is one reason there is no single timeless measurement called “the” feature size.
Why a modern “5 nm” or “4 nm” label is not a ruler
For decades, process-node names corresponded to the actual length of certain physical transistor features. The industry moved away from that practice while keeping progressively smaller nanometer labels. Intel’s Process Technology Naming article, reviewed February 14, 2025, explains this change. A current node label therefore does not establish that a particular gate, wire, or other chip feature measures that many nanometers.
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The 2020 IRDS Executive Summary offers a dated illustration: it gives a 36 nm tightest-metal pitch, whose half-pitch is 18 nm, and contrasts that historical metric with the industry’s “5 nm” generation label at the time. This is an example of why the label and a physical dimension are not interchangeable; it is not a present-day comparison of process technologies.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to compare chip processes meaningfully
When evaluating two process generations, start by identifying the actual dimension being reported. Compare the same metric in comparable product and process contexts—for example, gate length with gate length or metal pitch with metal pitch. A node number by itself does not prove that a specific physical feature is smaller or that one process is better.
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Physical dimensions are only part of a process comparison. Relevant considerations can also include transistor density, performance, power efficiency, cost, thermal management and the chip’s architecture and intended use. Intel lists these among characteristics that distinguish process technologies.
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