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Short answer: 130nm, 28nm and 7nm are process-generation labels, not a promise that every transistor feature has that exact dimension. Across these generations, transistor structures, achievable density, power and performance options, and design rules changed. But the label alone cannot tell you how fast, efficient, inexpensive or physically small a finished chip will be.
What does a process-node number mean?
A process node names a semiconductor manufacturing generation. It is not a reliable literal measurement of every transistor feature, such as gate length or pitch. Node naming has evolved, so a number by itself is not a common physical ruler for comparing processes from different foundries. Intel describes its node naming as reflecting a generation rather than a single feature dimension: Intel’s explanation of process-node naming.
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For a meaningful comparison, identify both the foundry and the exact process variant. In this article, the historical examples are TSMC processes: its 130nm generation, its 28nm high-performance mobile SoC process, and its N7 FinFET process. Another company’s “7nm” process is not automatically equivalent to TSMC N7.
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What changed from 130nm to 28nm to 7nm?
130nm: device choices and trade-offs were already important
TSMC’s 2003 discussion of 130nm and 90nm processes cautioned that device characteristics were no longer straightforward extensions of earlier generations. It highlighted mixed-signal design as an area where engineers had to consider device choices and trade-offs, rather than treating a node as one uniform transistor geometry. The 130nm label therefore does not describe every device available in that process or settle how a mixed-signal chip would behave. TSMC’s discussion of 130nm and 90nm process technology.
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28nm: high-k/metal gate, with planar transistors in TSMC’s sequence
A TSMC 2011 paper on a 28nm high-performance mobile SoC describes high-k/metal-gate technology and a broad range of power-to-performance options. That is a specific process variant and application example, not a description of every 28nm chip. TSMC says its logic processes remained planar until FinFETs entered production at 16nm in 2014. In other words, TSMC’s 28nm generation preceded its production transition to FinFET logic. TSMC’s 28nm high-performance mobile SoC paper.
Planar transistors form the channel in a relatively flat structure. As dimensions shrink, controlling the channel becomes more difficult. TSMC’s account of its process development describes FinFETs as improving electrostatic control at short gate lengths compared with planar structures, while also offering additional choices for balancing power and performance.
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7nm: TSMC N7 uses FinFETs
TSMC’s N7 is a FinFET process; TSMC says it entered volume production in 2018. That date applies to TSMC N7, not to every company’s process marketed with a 7nm label. TSMC’s logic technology overview.
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1Repair Windows errors before they cause bigger problems2Scan for outdated or missing drivers - takes under a minute3Clear out junk files and repair common Windows errorsDoes a smaller process node make a chip faster or more power efficient?
It can give chip designers new options, but it does not guarantee a particular product result. A finished chip’s speed and power depend on its architecture, circuit implementation, process variant, operating voltage, workload and design targets, among other factors. A process offering a wide power-to-performance range gives designers choices; it does not mean every design on that process will be faster or use less power.
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TSMC’s 2025 Annual Report illustrates the potential scale of change across selected TSMC processes. It reports normalized die-size and total-chip-power values, but these comparisons realign the logic/SRAM/I/O ratio. They are vendor-normalized comparisons for selected processes—not a prediction for arbitrary designs, and they do not include a 130nm point.
| TSMC process in the report | Normalized die size | Normalized total chip power |
|---|---|---|
| 55nm / N55LP | 1 | 1 (at 1.2V) |
| 40nm / N40LP | 0.48 | 0.6 (at 1.1V) |
| 28nm / N28HPM | 0.25 | 0.3 (at 0.9V) |
| 16FFC/12FFC | 0.11 | 0.07 (at 0.8V) |
| 7nm | 0.047 | 0.034 (at 0.75V) |
| 5nm | 0.035 | 0.022 (at 0.75V) |
| 3nm | 0.026 | 0.015 (at 0.75V) |
TSMC reports these normalized values in its 2025 Annual Report. Because the logic/SRAM/I/O ratio was realigned for the comparison, the figures do not mean that any arbitrary 7nm chip will use 3.4% of the power or occupy 4.7% of the die area of any arbitrary 55nm chip. They also cannot establish a 130nm-to-28nm ratio.
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What should you compare instead of the node number?
- Foundry and process variant: Compare named processes, such as TSMC N7 and TSMC N28HPM, rather than treating “7nm” or “28nm” as universal specifications.
- Transistor architecture: Establish whether the process uses planar transistors or FinFETs; architecture affects channel control and the design choices available.
- Density: Look for a stated density or a comparable die-size result, and check what logic, memory and I/O mix the comparison assumes.
- Performance and power: Require the operating conditions and design context. A voltage or normalized vendor figure is not a blanket guarantee for another chip.
- Design and manufacturing constraints: Process-specific rules, device options and implementation choices influence what can be built and what trade-offs are practical.
A newer, smaller-labeled process can enable denser or more efficient implementations, but the benefit is realized through a particular process and a particular chip design. Node labels are useful shorthand for generations; they are not stand-alone performance ratings.
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