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Gemma 4 QAT’s ability to run on one TPU v5e depends on the model size, checkpoint format, runtime, and memory needed beyond the weights. Google lists 16 GB of HBM per TPU v5e chip. Its approximate Q4_0 estimate for the 31B model is 17.5 GB, already above that capacity; the 26B A4B estimate is 14.4 GB, leaving limited room for runtime software and context-window KV cache. Smaller estimates make a model more plausible, but do not guarantee that a particular artifact and serving stack will work together.
Compare the model’s Q4_0 estimate with one chip’s HBM
Google’s Gemma 4 overview lists five model sizes and approximate inference-memory estimates by quantization. For Q4_0, those figures are:
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| Gemma 4 variant | Google’s approximate Q4_0 inference-memory estimate | What it means against one v5e chip |
|---|---|---|
| E2B | 2.9 GB | Below 16 GB, but runtime compatibility and additional memory needs still matter. |
| E4B | 4.5 GB | Below 16 GB, but not a guarantee of a working deployment. |
| 12B | 6.7 GB | Below 16 GB, but runtime compatibility and additional allocations still matter. |
| 26B A4B | 14.4 GB | Close to the 16 GB per-chip capacity, before software and context-window needs. |
| 31B | 17.5 GB | Exceeds the 16 GB per-chip capacity. |
The estimates are from Google AI for Developers’ Gemma 4 model overview; the per-chip capacity is from Google Cloud’s TPU v5e documentation. The overview describes these figures as approximate and says they may vary by inference tool and environment. They include a stated 20% overhead for loading additional things, but account only for static model weights: they exclude supporting software and context-window KV cache.
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“QAT” does not identify a single interchangeable file format. Google documents separate Gemma 4 artifacts for different deployment paths:
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-qat-q4_0-gguf: for llama.cpp or LM Studio local deployment.-qat-w4a16-ct: compressed-tensors W4A16 for vLLM or SGLang server deployment.-qat-q4_0-unquantized: for conversion or custom use.
These suffixes describe different artifacts and should not be treated as interchangeable. The engine pairings above are the ones in Google’s Gemma 4 overview. They do not, by themselves, establish that a GGUF artifact used with llama.cpp or LM Studio is supported on TPU v5e. Confirm that the chosen TPU runtime documents support for the exact artifact and deployment path; TPU serving documentation discusses its own stacks, including JetStream serving on TPUs with GKE.
Troubleshoot in this order
- Record the exact model and artifact. Note the variant and complete checkpoint suffix. Check whether you have the intended quantized collection, an unquantized QAT checkpoint, or a format meant for a different engine.
- Verify the runtime pairing. Match the artifact to its documented engine, then check the current documentation for the specific TPU runtime and deployment topology. A format being supported by an engine does not establish that every TPU stack supports that combination.
- Compare the estimate with capacity. One TPU v5e chip has 16 GB HBM. Google’s Q4_0 estimate for 31B is higher; the 26B A4B estimate is close enough that memory beyond the weights may be decisive.
- Reduce context length as a diagnostic. KV cache uses additional memory and grows with context. Shortening the context can help determine whether context-related allocation is contributing to a memory problem, but it does not guarantee the model will fit or resolve a runtime incompatibility.
- Account for software allocations. Leave room for the serving stack and other runtime needs; Google explicitly excludes supporting software from the estimates. The figures are not a promise that all available HBM can be used for model weights.
- Separate inference from fine-tuning. The table is an inference estimate, not a sizing guide for QAT or other tuning workloads. Google says tuning needs vary with method, framework, and batch size and are substantially higher than inference requirements.
When one chip is not enough
If a compatible configuration still does not fit, consider a smaller Gemma 4 variant or a larger TPU slice—but verify that the serving runtime and deployment topology support the exact model and artifact. Google Cloud documents one-, four-, and eight-chip serving configurations for v5e. Those infrastructure options do not establish that a particular QAT checkpoint will work unchanged across multiple chips.
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For runtime context, consult Google Cloud’s documentation for TPU v5e, training on TPU v5e, and running inference on Cloud TPU. Google also provides general guidance on running Gemma content generation and inference.
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- Performs high-speed ML inferencing: The on-board Edge TPU coprocessor is capable of performing 4 trillion operations (tera-operations) per second (TOPS), using 0.5 watts for each TOPS (2 TOPS per watt). For example, it can execute state-of-the-art mobile vision models such as MobileNet v2 at 400 FPS, in a power efficient manner. Works with Debian Linux: Integrates with any Debian-based Linux system with a compatible card module slot. Supports TensorFlow Lite: No need to build models from the ground up. TensorFlow Lite models can be compiled to run on the Edge TPU.
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- Performs high-speed ML inferencing: The on-board Edge TPU coprocessor is capable of performing 4 trillion operations (tera-operations) per second (TOPS), using 0.5 watts for each TOPS (2 TOPS per watt). For example, it can execute state-of-the-art mobile vision models such as MobileNet v2 at 400 FPS, in a power efficient manner.
- Works with Debian Linux: Integrates with any Debian-based Linux system with a compatible card module slot.
- Supports TensorFlow Lite: No need to build models from the ground up. TensorFlow Lite models can be compiled to run on the Edge TPU.
- Supports AutoML Vision Edge: Easily build and deploy fast, high-accuracy custom image classification models to your device with AutoML Vision Edge.
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