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A defensible estimate keeps those two cost types separate, defines a technical baseline, maps every activity in a work breakdown structure, uses current supplier data where possible, and shows how the result changes with schedule, process node, design reuse, iteration risk, and shipment volume. Public node figures are useful for scale, but they are not quotations for a particular design.
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Start with the two ASIC cost pools
The first estimating mistake is treating “ASIC cost” as one number. A project budget and a unit cost answer different questions.
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|---|---|---|
| One-time development/NRE | Product definition, architecture, RTL and analog/mixed-signal design, verification, physical implementation, EDA setup and compute, IP acquisition, packaging design, tape-out, masks, prototype lots, test development, qualification and post-silicon validation | Mostly incurred before production; some items can recur if the design is changed or a tape-out is repeated |
| Recurring production cost | Wafers, wafer sort, assembly, package materials, final test, production screening and other per-unit manufacturing charges | Scales with the number of wafers and finished devices |
Packaging and test can have both forms. Package selection, package design and test-program development are generally project costs; the package, assembly operation and test time for each finished device are recurring. Put each item in the pool that matches its behavior rather than forcing a supplier’s entire quote into NRE or unit cost.
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Fixed development cost is amortized economically, not paid again by the foundry for every unit. If NRE is F and lifetime shipments are Q, the NRE contribution per device is:
NRE per unit = F ÷ Q
The fully burdened unit economics are then the recurring manufacturing cost plus that amortized amount. A product with modest recurring cost can still be uneconomic at low volume when Q is small.
Why the development stack is so costly
Product definition and architecture require scarce expertise
Before RTL is written, a team must convert product requirements into an architecture: functions, interfaces, memory hierarchy, performance, power, area, safety or security features, package constraints and manufacturing targets. Architecture errors propagate into RTL, verification environments, physical design and software. Correcting one late can force broad rework, so experienced architects and system engineers are a significant part of NRE.
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The Semiconductor Industry Association (SIA) describes a path from product requirements and architecture through IC and packaging design, verification and post-silicon validation. Digital RTL, analog or mixed-signal blocks, clocking, power delivery, physical implementation and package interaction each require different skills. A small team may cover several disciplines, but the work itself does not disappear.
The OECD’s Mapping the semiconductor value chain (2025, p. 11) summarizes the cost drivers this way: “The costs of designing a chip vary widely depending on the feature size of the process node, the complexity of the design as well as license costs for EDA tools and IP cores.” The report characterizes modern design as involving more than 40 individual steps, with teams sometimes mixing tools across those steps. That is a description of process complexity, not a universal mandatory step count for every ASIC.
EDA tools and compute are recurring project commitments
EDA software supports simulation, synthesis, place-and-route, timing and power analysis, design-rule checking, layout-versus-schematic checks, formal verification and sign-off. The estimate should identify which tools are needed, for how many months, how many seats or tokens, and what compute or cloud capacity is assumed. A schedule extension can therefore increase both labor and EDA expense even when the design scope is unchanged.
Licensed IP trades engineering effort for contractual cost
Reusable CPU, SerDes, memory, interface, security and physical IP can shorten development and reduce the need to build specialized blocks internally. It may also require an upfront license, integration work, support fees and a per-unit royalty. The OECD notes that CPU and SerDes development requires specialized expertise, which helps explain why “reuse” is not cost-free.
PwC’s Semiconductor and Beyond 2026 estimates that IP license and royalty costs can represent 25–35% of an industry-leading project’s budget. That is a report estimate for a particular class of project, not a universal percentage. Your model should show upfront fees and royalties as separate lines so procurement can test both.
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The process node and PDK set the technical baseline
A process design kit (PDK) communicates a foundry’s design rules and manufacturing constraints to EDA tools. Choosing a different node or foundry changes those rules, available libraries, compatible IP, extraction models, design margins, packaging assumptions and often the verification burden. A late node change is therefore a baseline reset, not a simple price substitution.
Verification and sign-off consume time before fabrication
Verification must demonstrate that the implementation meets functional, performance, power and interface requirements across intended conditions. It can include simulation, formal methods, emulation, coverage closure, analog verification and sign-off checks. Physical sign-off adds timing, power integrity, electromigration, design-rule and manufacturability analysis. Underestimating verification staffing or duration is one of the quickest ways to make an early estimate obsolete.
Masks, prototypes and validation create large fixed commitments
The National Academies of Sciences, Engineering, and Medicine, in Strategies to Enable Assured Access to Semiconductors for the Department of Defense (2024, Chapter 2), identifies masks and the effort to design, verify, prototype and validate leading-edge designs as rising fixed-cost drivers. A first tape-out does not end the project: prototype assembly, bring-up, characterization, qualification and field-relevant validation still require people, equipment and time.
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A failed or incomplete tape-out can require another prototype lot or mask set. Do not insert a generic “respin price” into a budget; obtain a current foundry or design-service estimate for the target process and scope.
Low volume exposes the fixed-cost burden
Fixed costs are spread across output. The National Academies explains why low-volume production bears a heavier fixed-cost contribution per chip. The engineering budget itself does not shrink because a company ships fewer devices; rather, fewer devices share the same fixed investment. This is why volume must be modeled alongside NRE, not in a separate business case.
What published node figures can—and cannot—tell you
Published figures demonstrate the order of magnitude of advanced-node development, but they combine assumptions that may differ by source, year and project scope.
| Source and context | Published estimate | How to use it |
|---|---|---|
| SIA, “Chip Design and R&D”; figures described for the stated years | About $30 million for a 65nm chip in 2006; more than $540 million for a 5nm chip in 2020 | Historical scale reference; SIA describes the latter as more than an 18-fold increase over the former |
| PwC, Semiconductor and Beyond 2026, p. 53; approximate figures from expert interviews and PwC analysis | About $50 million at 28nm; $60 million at 22nm; $90 million at 16nm; $200 million at 7nm; $400 million at 5nm; $500 million at 3nm; $700 million at 2nm | Broad reference points, not quotations or a standardized node-cost series |
The SIA and PwC figures come from different publications and may use different definitions of design scope, staffing, IP, masks, prototypes and validation. Do not combine them into a single inflation-adjusted curve or present one as the price of your project. A supplier quote tied to your process, package, wafer volume and schedule is more relevant.
How to build a defensible ASIC estimate
1. Define the decision and the boundaries
State why the estimate exists: investment approval, make-or-buy analysis, product pricing, funding, or a node decision. Record the estimate date, currency, geography, planning horizon and target customer or shipment volume. Explicitly mark whether software and firmware, package qualification, safety certification, production ramp, field support and inventory are included.
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Use a written inclusion and exclusion list. “ASIC development” can otherwise mean only RTL through tape-out to one stakeholder and tape-out through qualified production to another.
2. Freeze a technical baseline
Describe the function and complexity of the device, performance, power and area targets, memory and interface requirements, target process and foundry, package, temperature or reliability conditions, and expected production life. Identify each major block as reused licensed IP, reused in-house IP, or new development. Record assumptions about die size, wafer size, expected yield and prototype quantity when data exists; label unknowns instead of silently assigning values.
3. Build a semiconductor-specific work breakdown structure
A work breakdown structure (WBS) makes omissions visible and gives each estimate an owner. A practical top level is:
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| Work package | Items to estimate |
|---|---|
| Product and architecture | Requirements, architecture, interface specifications, power/performance/area budgets and project management |
| IC implementation | RTL, analog/mixed-signal blocks, memory integration, clocking, power and physical design |
| Verification and sign-off | Testbenches, formal or emulation work, coverage closure, timing, power, reliability and manufacturability checks |
| EDA and compute | Tool licenses, support, seats or tokens, servers and cloud capacity for the planned schedule |
| IP | Upfront licenses, integration, customization, support and per-unit royalties |
| Packaging | Package selection and design, substrate or interposer work, thermal analysis and qualification preparation |
| Tape-out and prototypes | Foundry submission, masks, prototype wafers, assembly, bring-up boards and initial test fixtures |
| Production test | Test architecture, load boards, programs, characterization and per-device test charges |
| Post-silicon validation | Lab equipment, firmware, characterization, qualification and corrective iterations |
| Risk reserve | Schedule slip, scope growth, additional prototype lots or other explicitly modeled risks |
4. Estimate each work package using an appropriate method
For labor, estimate staffing by role and month, then apply a documented loaded cost that includes the items your organization normally burdens into engineering. For EDA, IP, foundry, mask, packaging and test, request current written estimates tied to the baseline. For internal equipment or cloud, use actual rates or approved procurement assumptions.
Use public node figures only as a sanity check. They cannot replace quotes because the scope, process, package, schedule and commercial terms may differ. The U.S. Government Accountability Office’s Cost Estimating and Assessment Guide (2020) recommends documenting data sources, methods and assumptions rather than presenting an unexplained point estimate.
5. Separate NRE from recurring economics in the financial model
Show at least these outputs:
- Total one-time NRE through a defined milestone, such as first qualified production.
- Recurring wafer, assembly, package and test cost per finished device.
- Cash timing by quarter or project phase.
- NRE amortization per unit at each shipment scenario.
- Total cost per unit and gross-margin impact after volume ramps.
Model low, base and high volume. If a business case uses an expected lifetime quantity, also show a downside case in which the product sells for a shorter period or ramps more slowly.
6. Run sensitivity and risk analysis
Vary the assumptions most likely to move the result:
- Schedule duration and staffing profile.
- Verification scope, coverage target and emulation or prototype needs.
- Amount of reused versus newly developed IP.
- Upfront IP fees, royalties and integration effort.
- Process node, foundry and package complexity.
- Number of prototype lots or tape-outs.
- Wafer yield, package yield and per-device test time.
- Low, base and high production volume.
Rank the changes by their effect on total NRE, launch date and unit economics. A sensitivity table is more useful to decision-makers than a single contingency percentage because it shows which decision could reduce exposure.
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7. Document confidence and update against actuals
Every line should have an owner, date, source, currency, scope and confidence range. Mark whether it is a supplier quote, an internal bottom-up estimate, an analogy or a broad benchmark. Reforecast when the node, package, IP contract, schedule or prototype plan changes. At each phase gate, compare actual labor, tool use, supplier invoices and schedule against the estimate, then record why the variance occurred.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.A worked volume example
The following numbers are illustrative arithmetic, not market rates or a quotation. Suppose a team builds a hypothetical device with $28 million of NRE and expects recurring wafer, assembly and test cost of $32 per finished unit.
| Lifetime shipment case | NRE amortization | Recurring cost | Illustrative fully burdened cost |
|---|---|---|---|
| 100,000 units | $280 per unit | $32 per unit | $312 per unit |
| 1,000,000 units | $28 per unit | $32 per unit | $60 per unit |
| 10,000,000 units | $2.80 per unit | $32 per unit | $34.80 per unit |
The manufacturing charge did not change in this simple illustration; only the number of devices sharing the fixed development investment changed. A real model would add yield, inventory, financing, warranty, distribution and price assumptions, but it should preserve the same separation.
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Use scenario comparisons to choose a viable path
When comparing a custom ASIC with another implementation or comparing two ASIC plans, evaluate the same axes for each case:
| Axis | Questions to answer |
|---|---|
| Upfront NRE | What engineering, EDA, IP, mask, prototype, package and validation work is required? |
| Recurring cost | What are wafer, assembly, package and test costs at the expected quantity? |
| Volume | How many units will ship, and over what lifetime? What happens if the forecast is cut? |
| Node and targets | Does the selected process actually meet performance, power and area requirements? |
| Schedule | How much verification, qualification and post-silicon work is needed before revenue? |
| Reuse and licensing | Which IP is reused, what integration remains, and are royalties acceptable? |
| Iteration risk | What is the technical and financial consequence of another prototype lot or tape-out? |
PwC discusses reusable in-house IP, chiplet or multi-node partitioning, open-source RISC-V and early EDA or foundry collaboration as possible levers. Treat them as options to evaluate against requirements, not guaranteed savings. Partitioning can add package, interconnect, verification and supply-chain work; open-source cores still require integration, verification and support.
Common estimating failures and how to correct them
Using a node headline as a project quote
Failure: Applying the $5nm or 3nm figure from a published report directly to a budget.
Correction: Use the figure only to challenge an implausibly small estimate, then replace it with bottom-up labor and current supplier inputs tied to your scope.
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Failure: Reporting one blended number without showing volume or cash timing.
Correction: Present NRE, recurring cost and amortization separately, with at least three shipment scenarios.
Leaving the technical baseline implicit
Failure: Estimating “a chip” without a node, package, performance target, IP plan or validation boundary.
Correction: Freeze those assumptions in a dated baseline and make every change trigger an estimate update.
Assuming reused IP is free
Failure: Omitting license, royalty, integration, verification and support costs.
Correction: Identify the contract terms and engineering work for every reused block.
Underfunding post-silicon work
Failure: Treating tape-out as the finish line.
Correction: Budget bring-up, characterization, qualification, test development, firmware support and corrective iterations explicitly.
Hiding uncertainty in an arbitrary contingency
Failure: Adding one percentage to cover every unknown.
Correction: Maintain a risk register, model specific drivers and show confidence ranges with named owners.
What a finance-ready estimate should contain
- A one-page scope statement with inclusions, exclusions, date, currency and geography.
- A technical baseline covering function, node, foundry, package, IP strategy and validation conditions.
- A WBS with labor, EDA, IP, foundry, masks, prototypes, packaging, test and validation.
- Separate NRE cash flow and recurring unit-cost model.
- Low, base and high volume scenarios.
- Supplier quotes or documented estimating methods for major external costs.
- Sensitivity results for schedule, node, IP, prototype iterations and volume.
- Confidence range, risk register, assumptions log and estimate owner.
- A schedule for refreshing the model as design and procurement facts firm up.
The practical answer to “How much does it cost to design an ASIC?” is therefore conditional. Costs rise with complexity, advanced process requirements, verification and validation scope, licensed IP, masks and iteration risk. A credible number is not a universal tariff; it is a traceable model that shows what is included, which assumptions drive it and how the economics change when production volume changes.
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