Tenstorrent and Japan’s Leading-edge Semiconductor Technology Center (LSTC) announced on February 27, 2024, that Tenstorrent’s RISC-V processor and chiplet intellectual property had been selected for an edge-AI accelerator intended for Japan’s 2nm semiconductor program. This is an ongoing design and commercialization effort—not a confirmed product launch.
Tenstorrent supplies licensed IP and co-design expertise. LSTC provides the open, collaborative research framework. Rapidus is the intended 2nm process and manufacturing partner, while Japan’s METI and NEDO programs provide institutional and financial support.
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What was announced
Tenstorrent said LSTC selected its RISC-V and chiplet technology for an “edge 2nm AI Accelerator,” in a multi-tiered partnership involving IP licensing and collaborative co-design. The announcement does not name a commercial chip, give a tape-out date, or publish specifications such as compute performance, memory capacity, power consumption or price.
Rapidus had already announced a separate agreement with Tenstorrent on November 16, 2023, to develop semiconductor IP for AI-edge devices based on 2nm logic. The LSTC project connects those design capabilities to Japan’s broader research and manufacturing strategy.
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Tenstorrent’s February 27, 2024 announcement describes the IP selection and accelerator target. Rapidus’s November 16, 2023 announcement describes the earlier joint-IP agreement.
The organizations have different jobs
| Organization | Role in the program |
|---|---|
| Tenstorrent | Provides RISC-V processor IP, chiplet IP, licensing and collaborative co-design support. |
| LSTC | Coordinates open, collaborative research covering circuit design, device technology, manufacturing methods, equipment and materials for 2nm and beyond. |
| Rapidus | Develops the advanced-logic process, pilot manufacturing and packaging path intended to support eventual production. |
| METI and NEDO | Provide policy, funding and program oversight within Japan’s semiconductor-revitalization framework. |
Japan’s METI framework distinguishes LSTC as the open collaborative R&D organization and Rapidus as the mass-production entity. That division matters: LSTC is not the foundry, and Rapidus is not merely a university-style research center.
What Tenstorrent is contributing
RISC-V processor IP
RISC-V is an open instruction-set architecture that allows designers to build customized processor implementations without depending on a proprietary instruction-set license. In this project, it could provide control processors or other programmable elements around the AI-compute subsystem. The announcement does not disclose the number of cores, extensions, operating frequencies or final system architecture.
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Chiplets divide a complex system into multiple dies that can be combined in one package. This can allow compute, memory, I/O and specialized functions to be developed or manufactured as modular building blocks. Potential benefits include architectural customization and IP reuse; the public materials do not establish the final chiplet topology, interconnect standard, packaging yield or cost.
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Licensing and co-design
Tenstorrent’s role is broader than selling a finished component. Its announcement describes IP licensing and collaborative innovation with the Japanese partners. The result is intended to be an edge-AI accelerator, but the final architecture and implementation schedule remain undisclosed.
What “2nm” means
“2nm” is a process-generation label, not a statement that every feature on the finished chip measures exactly two nanometers. Rapidus is developing a 2nm-class gate-all-around (GAA) logic process and has reported electrical operation of a 2nm GAA transistor on 300mm wafers.
Rapidus’s FY2026 program description also covers process-design-kit work, 2.xD and 3D packaging, RDL interposers, chiplet integration and manufacturing validation. None of those milestones proves that the specific Tenstorrent-LSTC accelerator has been fabricated or qualified.
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- ✅Enabling real-time, low latency and high-efficiency AI inferencing on the edge devices
- ✅Supports TensorFlow, TensorFlow Lite, ONNX, Keras, Pytorch frameworks
- ✅Supports Linux and Windows. Supports the temperature range of -40°C to 85°C
Where Rapidus stood by 2026
- April 2025: Rapidus began operating its pilot line at the IIM facility in Chitose, Hokkaido. Its IIM overview identifies the facility as the manufacturing hub for the 2nm effort.
- July 2025: Rapidus reported confirming electrical operation of a 2nm GAA transistor. Its corporate timeline places this in the broader process-development program.
- April 11, 2026: NEDO approved plans covering 2nm integration, short-turnaround manufacturing, chiplet packaging and related technologies.
- 2027 target: Rapidus continues to identify 2027 as its target for mass production, subject to the remaining process, yield, packaging and customer-validation work.
These are milestones for Rapidus’s overall 2nm manufacturing program. They do not establish a tape-out, wafer run, package test or production qualification for the Tenstorrent-LSTC accelerator.
What “edge AI” suggests—and what it does not prove
An edge accelerator is aimed at processing data near the device or network rather than sending every workload to a large cloud data center. Plausible application classes include automotive systems, robotics, industrial equipment, cameras, telecommunications infrastructure, local generative-AI or inference devices and consumer electronics.
Those are application categories, not announced customers. The partners have not published a target workload, benchmark, memory configuration, product partner or deployment schedule. “AI accelerator” also does not necessarily mean a conventional GPU; the final architecture remains undisclosed.
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No public evidence in the cited announcements establishes that the specific accelerator has been:
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- taped out;
- fabricated and packaged;
- benchmarked for performance or power;
- certified for a product;
- offered for purchase; or
- placed into volume production.
The accurate description as of 2026 is an ongoing R&D and commercialization program linked to Japan’s 2nm and chiplet ambitions. Rapidus’s pilot-line and transistor milestones show progress in the manufacturing platform, not completion of this particular AI design.
Why the partnership matters to Japan
Japan is trying to rebuild advanced-logic capability through a division of labor that combines public research, domestic manufacturing and international design expertise. LSTC gives universities, companies and research institutes a shared platform for technology development. Rapidus is intended to translate that work into foundry-scale production. Tenstorrent contributes an overseas AI and RISC-V design partner, while METI and NEDO support the program framework.
Rapidus announced a funding round totaling 267.6 billion yen on February 27, 2026, including a 100 billion yen investment from Japan’s Information-Technology Promotion Agency. The figures demonstrate strategic commitment, not guaranteed commercial success. Rapidus’s funding announcement provides the breakdown.
Potential advantages and unresolved risks
Potential advantages
- Japan-based advanced-semiconductor capacity and a more diversified supply chain.
- Customizable processor architecture based on RISC-V.
- Chiplet modularity for heterogeneous compute, memory and I/O.
- Closer coordination between chip architecture, process technology and packaging.
- An edge-AI focus that does not require copying a general-purpose data-center GPU.
Risks and open questions
- Design maturity: Has the project reached RTL completion, physical design, tape-out or silicon validation?
- Process readiness: Are the PDK, design rules, yield and defect density ready for external AI-chip customers?
- Packaging: Can a chiplet package be assembled with acceptable yield, bandwidth and cost?
- Software: Will Tenstorrent’s software stack support the intended edge workloads and deployment tools?
- Economics: Can wafer, packaging and test costs compete with established suppliers?
- Customers: Are there named automotive, robotics, industrial, telecom or consumer-electronics adopters?
- Schedule: Can the effort move from pilot manufacturing to qualified volume production by 2027?
How to evaluate future updates
The most useful evidence will be specific rather than promotional. Look for a named chip and tape-out date, silicon or benchmark results, disclosed power and memory figures, an identified package, independent customer validation, production yields, and a clear order or availability path. A new funding announcement, transistor milestone or partnership statement is important context, but none substitutes for those product-level proofs.
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What professionals can access today
The LSTC/Rapidus accelerator is not a retail product or a self-service cloud instance. Developers can instead evaluate Tenstorrent’s existing ecosystem through its official site and newsroom, including developer hardware and software offerings whose current stock and pricing vary.
Tenstorrent announced Wormhole cloud instances through Koyeb in February 2025. Cloud access can help with software experimentation, but it does not provide the future Japanese 2nm design.
Companies seeking a future manufacturing relationship can monitor Rapidus for PDK, foundry and packaging opportunities. No public standard wafer-price list or self-service purchasing plan has been established. EDA and design-service vendors such as Cadence, Synopsys, Siemens EDA and Arteris are ecosystem examples, not confirmed suppliers to this project.
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