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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Repair Windows errors before they cause bigger problemsFix Now →RDMA, SmartNICs and computational storage improve different parts of an AI data path. RDMA moves data between machines or accelerators while reducing host-CPU copying. SmartNICs and DPUs offload networking, security and storage services from that CPU. Computational-storage devices run selected filtering, transformation or inference operations near the data, so fewer bytes have to travel to a host or accelerator.
They are complementary architectural options, not three names for the same product and not a package every AI server must use. The right choice depends on whether your bottleneck is network transfer, infrastructure processing, storage traffic or the application itself.
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Start with the AI data path
An AI training or inference job repeatedly moves data through several stages:
- Datasets, checkpoints and logs reside on local or shared storage.
- Storage services deliver batches to a server.
- The server’s network adapter moves data between hosts, storage systems and accelerators.
- The host CPU coordinates protocols, security, memory copies and application logic.
- GPUs or other accelerators consume the data and return results.
A conventional path can require multiple copies: a device places data in host memory, the CPU processes or copies it, and a driver then transfers it to accelerator memory. CPU cycles, memory bandwidth, network latency and storage throughput can all become limiting factors. The three technologies in this article intervene at different points in that path.
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- RDMA changes how data is transferred across a network or fabric.
- SmartNICs and DPUs perform infrastructure work on or beside the network adapter.
- Computational storage performs selected work beside the storage media.
Removing a copy or an interrupt does not automatically make an end-to-end application faster. Protocol setup, topology, drivers, queueing, data preparation and the workload’s compute-to-I/O ratio still determine the result.
What RDMA does for AI systems
RDMA in plain language
Remote direct memory access (RDMA) lets a capable device transfer data to or from memory on another machine without routing every byte through the receiving host CPU’s ordinary copy path. The network adapter and software stack establish the connection, register memory and move payloads directly between permitted memory regions.
For distributed AI, that can reduce host-CPU involvement and intermediate memory copies when one server sends batches, gradients, parameters or activations to another. It can also help storage-to-accelerator paths when the storage and accelerator stack supports a direct data path.
RDMA is a capability, not a complete product stack
RDMA still requires compatible adapters, switches or fabrics, firmware, drivers, memory-registration support and application libraries. A direct transfer does not remove the need to configure addressing, congestion control, permissions, failure handling and monitoring. If any component falls back to a conventional path, the expected benefit may disappear.
RDMA can run over purpose-built fabrics or Ethernet-based RoCE implementations. AMD’s Embedded RDMA Enabled NIC: Applications, version 4.2 (released December 19, 2024), lists sensor-data transfer, video and image transfer, and remote-storage nodes over RoCE v2. Those examples show that RDMA is useful beyond one GPU vendor’s software stack; they are not a claim that every deployment is AI-specific.
RDMA for GPUs: keep the terminology precise
NVIDIA’s GPUDirect family includes technologies that allow network adapters and storage devices to read or write GPU memory under supported hardware and software configurations. GPUDirect RDMA describes direct communication between GPUs in remote systems and the network path. It is an NVIDIA implementation and ecosystem built on RDMA concepts, not a synonym for every RDMA deployment.
GPUDirect Storage addresses a different leg: moving data from supported storage devices toward GPU memory while avoiding unnecessary host-memory staging. A system can use ordinary RDMA without GPU memory, or use a GPU-direct path only where the complete compatibility matrix supports it.
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Where RDMA helps—and where it does not
- Potential fit: distributed training with frequent host-to-host exchanges, remote accelerator pools, high-throughput storage fabrics and inference services that exchange large tensors.
- Not a guarantee: small messages, CPU-bound preprocessing, an oversubscribed switch, poor congestion control or an application that cannot keep the transfer queues full.
- Operational requirement: test the entire path, including NIC firmware, switch configuration, kernel or runtime drivers, accelerator support and the framework’s communication library.
RDMA changes the transfer path; it does not make network capacity, GPU compatibility or storage performance irrelevant.
What SmartNICs and DPUs do
From a conventional NIC to an infrastructure processor
A conventional network interface controller connects a server to a network and handles packet transmission and reception. A SmartNIC adds hardware acceleration and often programmability for tasks such as virtual switching, telemetry, encryption, storage protocols or traffic shaping.
A data processing unit (DPU) is a programmable processor class intended to offload, accelerate or isolate data-centric services from the server’s main CPU. Depending on the product, a DPU can run networking, security and storage functions on its own cores and expose controlled resources to host workloads.
Names are not universal. One vendor’s “SmartNIC,” “DPU” or “SuperNIC” may differ in processor cores, memory, isolation model, accelerators and software support from another vendor’s device. Evaluate the documented functions rather than selecting by label alone.
Typical offloads
- Networking: virtual switching, packet processing, RDMA transport and traffic steering.
- Security: encryption, firewalling, tenant isolation, key handling and policy enforcement.
- Storage: NVMe-over-fabrics services, data movement and storage virtualization.
- Infrastructure control: telemetry, quality-of-service policies and management-plane functions.
Offloading these jobs can reserve host CPU cycles for model serving, preprocessing and orchestration. Isolation can also make a shared infrastructure service less dependent on the operating system that runs the application.
Examples and stated capability limits
NVIDIA identifies ConnectX SmartNICs and BlueField DPUs in its AI and GPU data-path material. Its DOCA software platform supplies libraries, services and management components for BlueField and ConnectX systems. The DOCA overview advertises connectivity of up to 800 gigabits per second (Gb/s) for the described platform. That is a vendor capability statement, not a universal SmartNIC speed or an independent workload benchmark; the actual rate depends on the specific adapter, port configuration, fabric and software.
What computational storage does
Compute near the data
Computational storage places selected processing functions in or near a storage device. Instead of sending every byte to the host CPU, the device may filter records, convert formats, decompress data, execute a narrow analytic operation or run a supported inference step before returning results.
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The goal is to reduce unnecessary data movement and host processing. For example, a device could discard records that do not match a query before they cross the storage bus, or transform a stored representation into the format expected by a downstream accelerator.
It is not an entire AI model inside an SSD
“Computational storage” describes an architecture and programming model, not a promise that a full training job or large language model runs inside a drive. The useful operation must be supported by the device’s processor, memory, firmware and API, and the operation must be worth performing there. Large, irregular or rapidly changing model workloads may still belong on host CPUs or GPUs.
Standards and interoperability
The Storage Networking Industry Association (SNIA) publishes a Computational Storage Architecture and Programming Model. The current page lists version 1.2, published April 21, 2026, and says: “The Computational Storage Architecture and Programming Model defines recommended behavior for hardware and software that supports Computational Storage.” SNIA’s Computational Storage Technical Work Group, updated April 2025, focuses on interoperability and common interfaces.
A standard improves the vocabulary and expected interfaces; it does not mean every computational-storage device supports the same instructions, data formats or performance. Verify the device API, supported operations, host drivers, orchestration tools and upgrade path before designing an application around it.
How the three technologies can work together
Consider a distributed inference service receiving images from remote storage:
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- Infrastructure offload: a SmartNIC or DPU handles network virtualization, encryption, storage services and traffic policy without consuming the model server’s main CPU.
- Direct transfer: an RDMA-capable path moves the remaining payload toward the target host or accelerator with fewer host-memory copies.
- Accelerator execution: the GPU runs inference and returns results through the network or storage service.
This is an architectural synthesis, not a required three-part design. A deployment may use RDMA without computational storage, a DPU without GPU-direct transfers, or computational storage in a server whose network remains conventional.
Comparison by layer and responsibility
| Technology | Where it acts | Work it can bypass or offload | Primary requirements | Main uncertainty |
|---|---|---|---|---|
| RDMA | Network or fabric data transfer | Host CPU copies and intermediate memory staging | RDMA-capable adapters, fabric, drivers, registered memory and application support | End-to-end compatibility, congestion and workload behavior |
| SmartNIC | Network interface | Packet processing, virtual switching, selected security or storage functions | Supported hardware accelerators, firmware, host integration and vendor software | Capabilities vary widely by model and vendor |
| DPU | Programmable infrastructure processor beside the host | Networking, security, storage and isolation services | DPU cores, memory, control-plane software and deployment tooling | Programming model, operational complexity and isolation boundaries |
| Computational storage | Storage device or storage appliance | Selected filtering, transformation or inference before host transfer | Supported device functions, APIs, drivers and orchestration | Interoperability and limited operation set; not every drive is computational |
Choose based on the actual bottleneck
When network movement dominates
Investigate RDMA when profiling shows that distributed workers spend substantial time exchanging large tensors or waiting on host-mediated copies. Confirm that the framework, accelerator runtime and network fabric can use the intended path. Measure application throughput and tail latency, not only link speed.
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When infrastructure consumes host CPU
Consider a SmartNIC or DPU when packet processing, encryption, virtual switching, storage services or tenant isolation compete with model execution. Define which services move to the device, how they are updated, and how operators will observe failures. Offloading a function that is rarely active may add complexity without meaningful relief.
When storage sends too much irrelevant data
Computational storage is most plausible when a simple, selective operation can eliminate substantial data movement: filtering, projection, decompression, format conversion or a narrowly defined inference step. Compare the device’s processing cost and capacity with the host CPU and network cost it replaces.
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When no single bottleneck is proven
Profile first. Collect storage queue depth, network utilization, host CPU time by service, memory-copy volume, accelerator idle time and end-to-end request latency. A faster network will not fix slow decoding; a DPU will not fix insufficient storage media; near-storage filtering will not help when the model itself dominates runtime.
Deployment requirements and failure modes
Compatibility is a matrix, not a checkbox
- Match adapter, accelerator, storage and switch capabilities.
- Check firmware, kernel, runtime, driver and communication-library versions together.
- Verify topology: PCIe placement, NUMA locality, switch paths and link rates.
- Confirm memory-registration, protection and tenant-isolation behavior.
- Document fallback behavior when a direct path is unavailable.
Common surprises
- CPU bypass with CPU work elsewhere: connection setup, protocol handling or preprocessing can remain expensive.
- Hidden copies: an unsupported buffer type or driver can silently stage data through host memory.
- Congestion: RDMA reduces copying, but an oversubscribed fabric still queues packets.
- Incompatible operations: computational storage may support filtering but not the exact format conversion or model operator required.
- Observability gaps: moving services onto a DPU changes where logs, metrics and security events are generated.
- Upgrade coupling: a new accelerator driver or firmware release can alter direct-path support.
Use controlled benchmarks that represent production message sizes, concurrency, failures and security policies. Report the complete configuration and workload; do not generalize from a headline link rate.
What the current evidence establishes
The cited vendor and standards material explains mechanisms, interfaces and product capabilities. It does not provide a neutral, directly comparable benchmark of RDMA, SmartNICs and computational storage together, nor an independent percentage improvement in performance, energy use, adoption or cost. NVIDIA’s GPUDirect page makes a “10X better performance” claim for GPUDirect RDMA, but without benchmark conditions alongside that claim it should be treated as a vendor statement rather than a general result.
The defensible conclusion is narrower and more useful: RDMA can reduce host involvement in transfers; SmartNICs and DPUs can move infrastructure services away from the main CPU; and computational storage can reduce data movement by processing selected data near storage. Their value depends on the workload, implementation and supported end-to-end stack.
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