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The clearest way to understand the portfolio is by the distance data must travel: scale-up links accelerators inside a compute domain, scale-out connects racks and domains within one data center, and scale-across links separate facilities over campus, metro, or regional distances.
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Marvell’s role in an AI data center
Marvell Technology is a semiconductor supplier. Cloud operators, server manufacturers, networking companies, optical-module makers, and storage-system vendors use its chips and intellectual property as parts of larger products. Marvell does not sell a complete AI data-center rack under this portfolio, and its switch silicon is not automatically a finished switch that an individual buyer can install.
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Its current infrastructure scope, as described in Marvell Technology, Inc.’s 2026 Form 10-K, includes custom ASICs, interconnects, Ethernet solutions, Fibre Channel adapters, processors, and storage controllers. The portfolio is broad because an AI cluster has several bottlenecks at once: accelerators need very short, high-bandwidth links; racks need a fabric to move traffic; storage and memory need controllers; and operators need security and telemetry.
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Marvell’s own description of its custom business is unusually specific: “We develop custom semiconductor solutions tailored to individual customer specifications that deliver system-level differentiation for next-generation artificial intelligence, data center, compute, networking, carrier, storage, aerospace and defense applications.” That is a company statement about its offering, not an independent assessment of market share or performance.
The three networking distances: scale-up, scale-out and scale-across
“Networking” in an AI facility is not one link type. The physical distance, protocol, latency target and optical or electrical medium change as traffic moves from an accelerator to another site.
| Layer | What it connects | Typical location | Marvell technologies identified for the layer |
|---|---|---|---|
| Scale-up | Accelerators and other compute elements in one compute domain | Inside a rack today, increasingly across several racks | PCIe, UALink, Ethernet and NVLink-related approaches; PCIe/CXL switching and retiming; custom die-to-die and chiplet links |
| Scale-out | Racks, servers and compute domains in one data-center cluster | Across racks and rows within a facility | Teralynx Ethernet switch silicon, PAM4 optical DSPs, drivers, TIAs, optical engines, AEC/AOC cable silicon and RELIANT telemetry |
| Scale-across | One data center to another | Campus, metro and regional links | Coherent and coherent-lite DSPs and COLORZ ZR/ZR+ pluggable modules |
Scale-up: keeping accelerators in one compute domain
Scale-up is the shortest-range layer, but it can be the most latency-sensitive. Marvell’s scale-up overview says: “Scale-up is the connectivity that couples accelerators into a single compute domain within a rack today and, increasingly, across several.” In practical terms, this is the path used when a distributed model or other workload needs accelerators to exchange data as though they were part of one tightly coupled system.
PCI Express remains a foundational host and peripheral interconnect. CXL extends PCIe’s physical foundation with memory-semantic capabilities, enabling systems to attach, share or pool memory resources. UALink is an industry effort aimed at accelerator connectivity. Ethernet and NVLink-related approaches address different parts of the same scale-up problem. Marvell’s materials identify all of these approaches rather than declaring one universal winner.
Marvell contributes components such as PCIe retimers, multiprotocol retimers and PCIe/CXL switches. A retimer receives a degraded high-speed signal, reconstructs it and retransmits it so a link can meet its electrical budget. A switch directs traffic among multiple ports and devices. Neither part, by itself, defines the complete server architecture; system designers choose the topology, protocol and software stack around it.
Scale-out: building the cluster fabric
Scale-out connects separate servers, racks and compute domains inside a data center. This is where an Ethernet fabric, optical transceivers, active cables and monitoring systems work together. Marvell identifies its Teralynx family as Ethernet switch silicon for data-center networking. A switch manufacturer can integrate that silicon into a finished switch, but the Teralynx chip is a component rather than a consumer-ready rack appliance.
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The physical links in a scale-out fabric may be copper for short reaches or fiber for longer reaches. Marvell lists PAM4 optical DSPs, coherent-lite DSPs, transmit amplifiers (drivers), transimpedance amplifiers (TIAs), optical engines, active electrical cable (AEC) and active optical cable (AOC) silicon, and the RELIANT telemetry platform for this layer. These products address different points in the link: signal conditioning, optical conversion, cable reach and operational visibility.
Scale-across: connecting separate facilities
Scale-across is the inter-site layer. It links data centers across a campus, metropolitan area or regional route, where fiber reach and optical efficiency matter more than a short copper connection. Marvell identifies coherent DSPs, coherent-lite DSPs and COLORZ ZR/ZR+ pluggable modules for these links.
On March 5, 2026, Marvell announced the COLORZ 1600 1.6T ZR/ZR+ pluggable, powered by its Electra 2nm coherent DSP, along with Libra, a 2nm 800G coherent DSP. Those are announced product developments and specifications from Marvell. They should not be read as proof of broad commercial shipment, customer adoption or an independently measured market lead; shipping status must be confirmed for the specific product and date.
How Marvell’s interconnect components move data
Interconnect is a system of components, not a single “AI networking chip.” Marvell’s portfolio page separates products by medium and function.
Electrical links and active cables
For short connections, Marvell lists AEC DSPs, active copper cable linear equalizers, PCIe retimers and multiprotocol retimers. Copper is attractive inside a rack because it can avoid an optical conversion for very short runs, but high data rates make signal loss and distortion harder to manage. A DSP or equalizer conditions the signal; a retimer restores timing and signal integrity; the cable assembly then carries the reconstructed data to the next device.
AOC silicon serves a similar systems role when the cable uses optical fibers. The module or cable maker, rather than the data-center operator, normally combines the silicon with connectors, lasers, photodiodes, firmware and mechanical packaging.
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Optical DSPs, drivers and TIAs
For fiber links, Marvell lists PAM4 DSPs, coherent and coherent-lite DSPs, laser drivers and TIAs. PAM4 encodes multiple signal levels per symbol to increase electrical or optical throughput, while the DSP compensates for channel impairments and manages the transmit and receive signal path. A laser driver controls the optical transmitter; a TIA converts the tiny current from a photodetector into a usable electrical signal.
Marvell also lists silicon photonics, co-packaged optics and linear pluggable optics components. These represent different ways of placing optical engines and electronics in relation to a switch or accelerator system. The choice affects reach, power, serviceability, thermal design and the ability to upgrade a module independently from the switch.
What “DSP” means in this context
A digital signal processor in a high-speed link is not a general-purpose CPU. It performs equalization, clock and data recovery, modulation or demodulation functions, error handling and related signal processing so data can cross an electrical or optical channel with acceptable integrity. The required implementation depends on the protocol, reach and medium. Comparing two DSPs only by a headline data rate would omit power, error margin, optics, cable type and system-level constraints.
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Switch silicon determines how packets or memory transactions move among ports. Marvell’s Teralynx family targets Ethernet data-center fabrics. Its broader portfolio also includes Structera CXL switches for memory pooling and Bravera SSD controllers for storage-related workloads.
A CXL switch can let several hosts access a shared pool of memory devices, subject to the capabilities and software policy of the complete system. That is different from an Ethernet switch, which forwards packets between network endpoints. Both may appear in the same AI infrastructure design, but they solve different communication problems.
RELIANT is described by Marvell as a telemetry platform for scale-out environments. Telemetry gathers operating data—such as link health, congestion or errors—so operators can diagnose a fabric and tune workloads. It is an operational layer around the switching and interconnect hardware, not a replacement for either.
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Custom ASICs: co-design instead of a catalog part
Merchant silicon is designed for a broad set of customers and standardized interfaces. A custom ASIC is co-designed around one customer’s system requirements, workload and deployment strategy. Marvell combines its reusable intellectual property, design services, packaging and manufacturing relationships with those requirements.
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What Marvell says it can integrate
- High-speed SerDes for electrical and optical interfaces.
- Arm compute subsystems for control or application processing.
- Security functions, including root of trust, key management and cryptographic acceleration.
- Storage and networking functions tailored to a particular architecture.
- Silicon photonics and optical I/O.
- Die-to-die links and chiplet interfaces.
- Custom high-bandwidth memory (HBM) arrangements.
- Advanced packaging that combines multiple dies or optical and electrical elements.
The benefit is system-level differentiation: a customer can optimize a chip for its own topology, software and power envelope rather than selecting a general-purpose part. The trade-off is a longer design cycle, substantial nonrecurring engineering cost and dependence on a specific manufacturing and packaging plan. A custom ASIC therefore cannot be evaluated like an off-the-shelf network adapter.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Memory, storage and security around the accelerators
AI infrastructure also needs to feed data to accelerators and protect it. Marvell’s portfolio includes CXL switches for memory pooling, SSD controllers, Fibre Channel adapters and controllers, hard-disk-drive controllers and preamplifiers, and storage accelerators.
These products are not all exclusive to AI data centers. The same storage controller or Fibre Channel technology may serve enterprise, cloud, carrier or other infrastructure. Their relevance to AI is architectural: training and inference systems require high-throughput storage paths, predictable access to datasets and reliable movement between compute and memory tiers.
In custom silicon, Marvell describes root-of-trust, key-management and cryptographic acceleration capabilities. A root of trust establishes a hardware foundation for verifying firmware and system components. Key management protects cryptographic material, while acceleration reduces the processing burden of encryption or authentication. The exact security design depends on the customer’s threat model and software stack.
Which products are current, and which are still developing?
Marvell’s 2026 Form 10-K distinguishes current offerings from products in development. It lists custom ASICs, interconnects, Ethernet solutions, Fibre Channel adapters, processors and storage controllers among current offerings. The filing also says Marvell is developing UALink switches and Ethernet for Scale-Up Networking (ESUN) switches.
That distinction matters. A public announcement, development program or roadmap is not evidence that a product is shipping at scale, available through a normal channel or supported by a particular server. Buyers need to confirm sampling, production status, software support, approved systems and regional availability directly with the relevant vendor.
Marvell completed its previously announced acquisition of Celestial AI on February 2, 2026, adding Photonic Fabric technology. The same filing says XConn extends Marvell’s switch portfolio with PCIe and CXL switches. These transactions expand the technologies Marvell can offer, but they do not mean every resulting product is already a generally available component.
How to compare the competing scale-up approaches
Marvell’s scale-up material names PCIe, UALink, ESUN, Ethernet and NVLink-related approaches. The industry has not settled on one approach for every AI architecture. A useful comparison uses four questions rather than a blanket winner.
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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstall| Decision axis | What to ask |
|---|---|
| Bandwidth | How much aggregate traffic must pass between accelerators, memory devices and hosts, and is the figure per lane, port or complete system? |
| Latency | Does the workload require tightly coupled accelerator communication, or can it tolerate fabric and protocol overhead? |
| Openness | Can multiple vendors supply the interface, switches, software and accelerators, or is the design tied to a narrower ecosystem? |
| Deployment readiness | Are compliant switches, cables, firmware, drivers and validated systems shipping for the intended date and region? |
The right answer depends on the operator’s accelerator mix, software, rack topology, power budget and procurement strategy. Announced interoperability or a high headline rate does not by itself establish production readiness.
What Marvell makes—and what it does not
- It makes: semiconductor chips, optical and electrical link components, switch silicon, controllers, security functions, custom ASICs, chiplet and packaging technologies, and related platforms such as telemetry.
- It enables: scale-up accelerator domains, scale-out Ethernet fabrics, scale-across optical links, memory pooling and storage connectivity.
- It does not necessarily make: a complete AI server, a finished rack switch, a universal optical transceiver sold to consumers, or a turnkey data center.
For a systems architect, the useful question is not “Which Marvell box should I buy?” It is “Which Marvell component or custom design fits the link, protocol, reach, thermal envelope and software stack in the system I am building?”
Quick Recap
Practical checklist for evaluating a Marvell-based design
- Classify the distance. Decide whether the link is scale-up, scale-out or scale-across before comparing parts.
- Identify the medium. Choose between copper, active electrical cable, optical fiber, co-packaged optics or a pluggable module based on reach, power and service requirements.
- Name the protocol. Record whether the path uses PCIe, CXL, Ethernet, UALink, ESUN, an NVLink-related interface or a custom die-to-die link.
- Separate chip from system. Confirm which company supplies the finished switch, cable, optical module, firmware and management software around Marvell silicon.
- Check maturity. Verify sampling, production, interoperability and support dates; treat UALink and ESUN switches as in development where the 2026 Form 10-K does so.
- Model the whole link. Include optics, retimers, connectors, cooling, error handling, telemetry and software—not just the DSP or switch’s advertised rate.
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