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2D semiconductors are not missing from commercial chips because researchers cannot make a working transistor. They are missing because a commercial chip requires a complete, repeatable, CMOS-compatible process: uniform material across a wafer, low-defect films, scalable contacts, controllable n-type and p-type behavior, reliable gate stacks, acceptable thermal and contamination budgets, high yield, and stable operation over time. Research devices have demonstrated impressive current, speed and switching ratios, but those isolated results do not yet amount to a production-qualified manufacturing flow.
Transition-metal dichalcogenides (TMDs), particularly molybdenum disulfide (MoS2), remain a promising option for very small channels. Their atomically thin bodies can improve electrostatic control when conventional silicon channels become difficult to scale. The unresolved question is whether that channel advantage can survive every other step needed to build billions of matching transistors on wafers.
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What a commercial 2D chip process must accomplish
A laboratory transistor can be judged by a few headline metrics. A chip factory must control the entire distribution of results. Every wafer and lot needs predictable dimensions, composition, threshold voltage, contact resistance, leakage, switching behavior and lifetime. The process also has to fit existing lithography, interconnect, dielectric, cleaning and inspection equipment without introducing contamination or exceeding temperature limits.
- Material uniformity: thickness, crystal orientation, composition and defect density must remain within narrow limits across a wafer and from wafer to wafer.
- Electrical repeatability: transistors must have similar threshold voltages, mobility, contact resistance and leakage so circuits can be designed with useful margins.
- CMOS compatibility: the process must support complementary n-type and p-type devices, not just a high-performing transistor of one polarity.
- Integration: contacts, gate dielectrics, spacers, passivation and metallization must work together at acceptable temperatures and contamination levels.
- Manufacturing economics: transfer, growth, patterning, inspection and repair steps must be fast enough and reliable enough to produce a high fraction of working dies.
- Reliability: electrical characteristics must remain stable under bias, temperature cycling and long operating times.
The International Roadmap for Devices and Systems (IRDS) summarizes the device-level priorities this way: “The state-of-the-art electronic properties of TMD FETs, as well as their yield, variability, and reliability, may be further enhanced if progress is achieved in mainly five directions: channel fabrication, doping, source/drain contact resistance, gate dielectric, and variability.” Those five areas are connected; improving one while neglecting the others does not produce a manufacturable logic process.
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Wafer-scale growth still produces too much variation
Coverage is not the same as a usable semiconductor film
Chemical vapor deposition (CVD) and molecular beam epitaxy (MBE) can create large-area TMD coverage. However, a continuous-looking film may still contain thickness variation, vacancies, impurities and boundaries between crystal domains. A monolayer that is one atomic layer in one region and locally thicker elsewhere will not have identical band structure or gate control. Vacancies and other point defects can act as traps or scattering centers, reducing mobility and worsening reliability.
The 2026 National Science Review synthesis links grain boundaries, vacancies and thickness variation to both within-wafer and wafer-to-wafer electrical variation. That variation directly affects circuit yield: a few exceptional devices do not compensate for a broad distribution of weak or unstable ones.
Crystal orientation creates hidden electrical barriers
Many large-area films are made from multiple domains. Where domains with different crystal orientations meet, the boundary can scatter carriers and create a locally different barrier. The 2024 IRDS review notes that many single-crystal demonstrations remain micrometre-scale and that wafer-level single-crystal quality was rarely achieved in the work it examined. For a commercial wafer, domain boundaries must either be eliminated, placed harmlessly, or characterized well enough that circuit designers can tolerate them. None of those options is routine for 2D channels today.
Inspection and process control are not solved by making the film thinner
Because the active layer may be only one or a few atomic layers thick, conventional thickness and defect metrology cannot simply be assumed to work as it does for bulk silicon. Manufacturers need fast, non-destructive ways to map layer count, contamination, wrinkles, cracks, grain structure and electrical uniformity before committing a wafer to many later process steps. Wafer-scale defect statistics and uniformity data remain unavailable in a comparable, current data set demonstrating production-level control.
Transfer and direct growth involve different manufacturing risks
Researchers commonly grow a TMD on a source substrate and then transfer it to the wafer where the transistor will be built. That approach can produce excellent material because the growth substrate is optimized independently of the CMOS wafer. Its manufacturing cost is a sequence of additional handling steps, alignment, cleaning and bonding.
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Why transfer is attractive—and problematic
- Growth can occur at temperatures and on surfaces that produce better crystals than a finished CMOS wafer would allow.
- Transfer separates material synthesis from transistor fabrication, giving researchers more flexibility in selecting substrates.
- Polymer scaffolds and other transfer supports can leave residues or introduce wrinkles, tears, trapped moisture and particles.
- Large-area transfer is slow and can vary from wafer to wafer; defects created during handling may be difficult to detect before patterning.
The IRDS report specifically identifies polymer-related impurities, process slowness and variability as transfer concerns. An excellent transistor made after a carefully controlled small-area transfer therefore does not establish that the same transfer can be repeated economically across production wafers.
Why direct growth is appealing
Directly growing a TMD on a CMOS-processed silicon wafer could remove several transfer steps and reduce handling damage. One route discussed by the IRDS uses a two-temperature-zone CVD or metal-organic CVD arrangement: high-temperature chemistry is generated in one zone, while deposition occurs at a lower temperature near the CMOS wafer. This concept addresses integration, but it does not automatically deliver the same electrical performance as material grown on an ideal research substrate.
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| Integration route | Potential advantage | Manufacturing difficulty |
|---|---|---|
| Grow then transfer | Growth substrate can be optimized for crystal quality and device performance. | Residue, tears, wrinkles, particles, alignment steps, slow handling and transfer-to-transfer variation. |
| Direct growth on a processed wafer | Fewer transfer operations and a clearer path to monolithic integration. | Thermal budget, contamination, nucleation control and lower demonstrated current in the cited example. |
Contacts remain a central bottleneck
Even when the channel itself transports carriers well, the metal-to-semiconductor interface can limit the transistor. Contact resistance and carrier-injection barriers reduce current, increase delay and consume voltage headroom. A contact process must provide low resistance while remaining compatible with tiny dimensions, alignment tolerances, thermal cycles and repeated fabrication.
Low contact resistance must survive scaling
A 2024 National Science Review perspective reports a 42 Ω·µm contact-resistance result for an antimony (Sb) contact on monolayer MoS2. That is an important research result, but it does not by itself prove an integrated-circuit contact process. Some very low-resistance demonstrations use micrometre-scale contact lengths, which provide more area for carrier injection. The same perspective points to an advanced-node IRDS requirement of sub-20-nm contact length. Shrinking the contact can increase resistance, make edge alignment more critical and expose variability that is hidden in a long-contact experiment.
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Interface engineering has trade-offs
Semimetals, edge contacts and van der Waals interfaces can reduce barriers, but each introduces new requirements for deposition, cleanliness, patterning and thermal stability. A contact that is electrically excellent on a fresh flake may react, diffuse or degrade during subsequent dielectric and interconnect processing. Production qualification therefore needs contact distributions at the intended geometry, not only the best value from a large test structure.
CMOS needs controllable complementary polarity
Modern logic relies on complementary metal-oxide-semiconductor (CMOS) circuits, pairing n-type and p-type transistors so that static power is low and logic levels are robust. The IRDS examples are dominated by n-type MoS2 devices; true complementary integration has been limited. Demonstrating a single high-current n-type transistor is therefore not enough to replace a silicon logic platform.
Doping must be stable and selective
Charge-transfer doping can shift threshold voltage and increase current in experimental devices. Excessive doping, however, can prevent a transistor from turning off, raising leakage and destroying logic noise margins. A manufacturing process must place the right dopant or charge-transfer layer in the right region, control its concentration, survive later thermal and chemical steps, and remain stable over the product lifetime.
Contacts do not equal channel doping
Contact metals influence which carriers are injected and can make a device appear more n-type or p-type. That effect is not the same as uniformly and controllably doping the channel. The IRDS discussion distinguishes carrier injection at contacts from channel doping; choosing a different metal alone does not solve threshold control, complementary performance or long-term polarity stability.
For practical CMOS, n- and p-channel devices also need sufficiently matched drive current, threshold distributions and reliability. If one polarity is much weaker or more variable, circuit designers must add area or accept lower speed and yield.
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Gate dielectrics, spacers and interfaces can erase the channel advantage
An atomically thin channel is highly sensitive to its surroundings. The gate dielectric must provide strong electrostatic control without introducing interface traps, remote scattering, fixed charge or chemical damage. Depositing a uniform dielectric on an inert 2D surface can be difficult because the surface lacks the dangling bonds that help conventional films nucleate.
Published sources identify dielectric integration, spacer design, passivation and interface states as unresolved concerns. The 2026 review also highlights dielectric-polarization impurities and the lack of compatible low-k spacer processes. Traps can shift threshold voltage, cause hysteresis and increase noise; impurities or roughness can reduce mobility; an unsuitable spacer can increase parasitic capacitance and slow the circuit.
Passivation must protect the channel from oxygen, moisture and processing chemicals while remaining compatible with lithography and later metallization. A gate stack that works in an isolated research transistor may fail when exposed to plasma cleans, multiple anneals or the mechanical stress of a full interconnect flow.
The complete process must fit a CMOS fab
Thermal budget and contamination control
Many high-quality 2D films require growth or annealing conditions that are difficult to apply after temperature-sensitive transistors and interconnects already exist. Conversely, lowering the temperature can reduce crystal quality or change nucleation. The 2026 review discusses below-400 °C processing as a BEOL-compatible direction, not as a universal demonstrated manufacturing threshold. A viable process must show that its actual temperature history, gases, catalysts and residues are acceptable for a defined fab flow.
Lithography, alignment and metallization
Wafer-scale 2D integration still has to align source, drain, gate, spacers and contacts over a film that may contain wrinkles or domain boundaries. Etching can damage an atomically thin channel or leave residues at the contact edge. Metallization must adhere, remain chemically stable and meet electromigration and reliability requirements. These interactions make the process-flow problem larger than simply depositing a 2D sheet.
Monolithic 3D integration is promising but unproven
Because 2D layers can be transferred or grown at relatively low temperatures, they are often discussed for monolithic three-dimensional integration above completed silicon circuitry. Proposed routes include low-temperature BEOL-compatible contacts and dielectrics, automated transfer, wafer bonding and selective-area growth. The 2026 review presents these as directions under study; they are not evidence that a volume-production flow has been qualified.
Variability, yield and reliability determine commercial readiness
A readiness claim should report more than a champion transistor. Manufacturers need wafer maps and statistical distributions showing defect density, layer thickness, threshold voltage, on-current, off-current, contact resistance and breakdown behavior. They also need lot-to-lot repeatability, circuit-level yield, alignment tolerance and the fraction of dies that pass after all process steps.
- Variability: measure within-wafer, wafer-to-wafer and lot-to-lot distributions rather than a single best device.
- Yield: report working transistor arrays and circuits after the complete flow, including known-good-die statistics.
- Reliability: track threshold drift, bias-temperature stress, dielectric breakdown, contact degradation and environmental stability.
- Process compatibility: disclose thermal history, contamination controls, lithography and metallization assumptions.
- Scalability: demonstrate the intended contact length, gate length, wafer size and throughput, not only enlarged laboratory structures.
Current literature identifies these measurements as essential, but the available sources do not provide a comparable contemporary data set proving production-compatible wafer-scale yield for 2D transistor modules.
What the headline research numbers do—and do not—prove
| Reported figure | Context and limitation |
|---|---|
| 1.23 mA/µm on-state current at 1 V drain-source bias; 74 fs intrinsic delay; on/off ratio above 108 | MoS2 device study summarized by the 2024 IRDS. The channel was transferred and the gate dielectric was HfO2; this was not a production-fab result. |
| About 3 µA/µm maximum on-state current | Specific direct-growth-on-CMOS-wafer example summarized by the 2024 IRDS. It is not a universal ceiling for direct growth. |
| 42 Ω·µm contact resistance | Reported Sb/monolayer-MoS2 contact demonstration in a 2024 National Science Review perspective; scaled geometry and full-flow manufacturability remain separate questions. |
| Sub-20-nm contact length | Advanced-node IRDS roadmap requirement cited by the 2024 perspective, not a measured industry-wide production figure. |
| 0.7-nm node in 2034 | IRDS roadmap projection reported in 2024; it is not a guarantee that commercial 2D chips will exist by that date. |
What would show that 2D chips are ready?
A credible transition from research to manufacturing would combine a uniform wafer-scale channel with a complete process module and statistical evidence. The decisive demonstration would include:
- A defined wafer size and growth or transfer method with mapped thickness, grain structure, vacancies and contamination.
- Repeatable source/drain contacts at the intended sub-20-nm-class geometry, with resistance distributions rather than a single record.
- Stable n-type and p-type devices, including threshold control and matched performance for complementary circuits.
- A gate dielectric, spacer and passivation stack that survives the planned thermal, plasma and chemical sequence.
- Integrated logic arrays showing circuit yield, speed, leakage and noise margins after the full process.
- Reliability data under electrical and thermal stress, plus wafer-to-wafer and lot-to-lot reproducibility.
Until those pieces are demonstrated together, 2D channels should be viewed as a research and future-integration option rather than a broad commercial replacement for silicon. Their ultrathin geometry may become valuable at dimensions where electrostatic control is difficult, but manufacturing—not the absence of an impressive transistor—is the barrier that still separates laboratory success from dependable chips.
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