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A quantum computer is scalable when its useful, error-corrected computational capacity can grow without costs and engineering problems overwhelming the system. A large physical-qubit count is only one input. A credible scale claim should show how many logical qubits can run at once, how long they remain reliable, which operations they support, how quickly correction and feedback run, and whether control hardware, cooling, software and classical infrastructure can expand with the machine.
What “scalable” means in quantum computing
Scalability is the ability to increase useful computational capacity while preserving reliability, programmability and practical operating cost. In a quantum processor, growth can fail at several points: additional qubits may be too noisy to use, wiring and control may become unmanageable, error-correction data may overwhelm the decoder, or a circuit may become so deep that errors accumulate before the answer is measured.
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IBM Quantum’s June 2025 description proposes six properties for a scalable architecture: fault-tolerant, addressable, universal, adaptive, modular and efficient. These are a vendor-authored framework, not a standards-body definition. They are useful because they force a scale discussion beyond a single qubit total.
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Fault-tolerant
Fault tolerance means that error-correction procedures suppress logical errors enough for a useful algorithm to complete. The relevant evidence is not a one-time state-preparation snapshot. It is repeated correction during computation, with logical error behavior measured over multiple cycles and operations.
Addressable
Every logical qubit and the operations involving it must be controllable and measurable without unacceptable interference from the rest of the processor. A device can contain many physical qubits yet offer only a small simultaneously usable subset if calibration, crosstalk or readout limitations prevent independent control.
Universal
A scalable machine must support a gate set capable of expressing the algorithms it claims to target. Demonstrating one specialized operation or circuit family does not establish universal computation. Claims should state which logical gates, measurements and state-preparation procedures were actually demonstrated.
Adaptive
Useful error correction and many algorithms require decisions based on measurement results. The control system must acquire results, decode them and apply feed-forward operations quickly enough that the computation does not stall. Adaptive capability therefore includes classical control latency, decoder throughput and the interface between quantum and classical hardware.
Modular
Modularity allows capacity to grow by connecting processor modules rather than placing every qubit in one monolithic device. The connection must preserve fidelity, timing and addressability; simply adding a network link does not prove that modules can participate in a useful algorithm.
Efficient
Efficiency covers the resources required per useful logical operation: physical-qubit overhead, control channels, cryogenic and electrical power, decoding compute, calibration time, footprint and algorithmic runtime. A system that scales only by multiplying impractical support equipment is not practically scalable.
Why physical-qubit count is not enough
A physical qubit is a controllable hardware element. A logical qubit stores encoded information across one or more physical qubits, depending on the error-correction code and protection level. The two quantities are not interchangeable. A processor with a large physical register may have few logical qubits, or none that can sustain a long algorithm.
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When a company reports “logical qubits,” ask what code and protection procedure produced the number, how many physical qubits were consumed, what logical error rate was measured, and under what operating conditions. Also ask whether the logical qubits were available simultaneously and whether they supported the operations required by the proposed application.
A credible logical-qubit result normally includes repeated error-correction cycles, logical state preparation and measurement, and a demonstration that error is suppressed as protection resources increase. It should identify the supported gate set, code distance or equivalent protection parameter, decoder, feedback path and test duration. A single encoded state that survives one short experiment is not evidence of scalable computation.
What error-correction evidence to look for
Repeated correction, not a single snapshot
Scalable machines must correct errors throughout a computation. Look for results across many cycles, not merely before-and-after fidelity. The report should show how logical error changes when code distance or other protection resources are increased. If larger codes do not reduce the logical error under comparable conditions, adding more physical qubits is not yet producing the expected scaling behavior.
Operations that match the intended algorithm
Preparation, measurement, single- and two-qubit logical gates, routing and mid-circuit measurement can have different error profiles. A claim based only on memory storage does not establish that the processor can run a gate-intensive algorithm. Ask which operations were fault tolerant, how they were compiled and whether classical feed-forward was included.
Real-time decoding and feedback
Error syndromes generate classical data that must be decoded while the computation proceeds. Microsoft authors Matthias Troyer, Chetan Nayak and John Martinis proposed this definition in September 2026: “To make the progress on logical qubits measurable and comparable we introduce the definition of scalable logical qubits: logical qubits preserved for long computations by repeated quantum error correction, capable of fault-tolerant universal operations with low-latency real-time decoding and feedback, and replicable to the hundreds or thousands, as required by applications.” This is a vendor proposal, not an industry consensus rule. It highlights why decoder latency and feedback are part of the scale claim.
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Calibration drift, thermal changes and component variation can reduce the number of qubits that remain usable. Request the measurement date, run duration, recalibration policy and uncertainty. A peak result obtained during a brief, heavily tuned experiment should not be presented as a continuously available capacity.
System engineering determines whether a design can grow
The U.S. Department of Energy’s 2024 roadmap describes large-scale fault-tolerant computing as a full-stack challenge involving materials and devices, packaging, control, cryogenics, interconnects, error correction, software, system engineering and algorithms. This matters because each layer can become the bottleneck even when the qubit device itself performs well.
- Wiring and control electronics: More qubits require more signals, filters, amplifiers and timing channels. The architecture must avoid an unmanageable cable and connector count.
- Cryogenics and power: Cooling capacity, heat load and room-temperature electronics must grow with the processor without disturbing qubit conditions.
- Packaging and interconnects: Larger devices need repeatable connections between chips or modules while preserving signal integrity and low error rates.
- Classical compute: Decoders, schedulers, compilation and experiment orchestration may require substantial low-latency processing alongside the quantum hardware.
- Software: Compilers must map logical circuits onto available connectivity, manage routing and expose the measured error model to users.
- Modularity: A modular design needs a demonstrated way to create high-fidelity links and coordinate timing across modules.
A scale claim should therefore state the boundary of what was measured: the qubit chip, a complete cryogenic stack, a networked module, or an end-to-end service. Results from one layer cannot automatically be generalized to the whole system.
How to measure quantum-computer performance
Different metrics answer different questions. Report the circuit, compilation method, success criterion and measurement conditions with every score.
Width and depth
Width is the number of qubits used simultaneously. Depth is the number of sequential layers in a circuit. A wide, shallow circuit stresses parallel control and readout; a narrow, deep circuit stresses coherence, correction and accumulated error. Always report both, and specify whether the count refers to physical or logical qubits.
Gate totals also need a definition. “5,000 gates” could mean total gates, two-qubit gates, logical gates or another operation. Routing and SWAP operations inserted by the compiler can materially increase the work beyond the algorithm’s abstract circuit.
Circuit-layer operations per second (CLOPS)
CLOPS measures the rate at which a system executes layers of parameterized circuits, including relevant control and reset activity under the stated protocol. It is a throughput metric, not a direct measure of answer quality or fault tolerance. IBM Quantum reported more than 150,000 CLOPS in a 2024 performance account; the figure is a company-reported result for its stated demonstration.
Quantum Volume
Quantum Volume combines circuit width and depth under a defined protocol. IQM’s documentation describes it around the deepest circuit a given number of qubits can run with meaningful results. Because the protocol, compilation and success threshold matter, Quantum Volume scores from different versions or measurement procedures should not be treated as automatically comparable.
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Error and fidelity measures
Gate, readout and logical error rates describe reliability. Ask whether the value is an average, a worst case or a selected best result; whether it was measured on all qubits or a subset; and whether mitigation, postselection or classical correction was used. A lower physical error rate is valuable, but it does not by itself establish that a large logical computation is feasible.
How to evaluate a quantum-computing scale claim
- Identify the unit. Write down whether the headline number means physical qubits, logical qubits, modules, total gates, logical gates, circuit layers or operations per second. Record how many units were simultaneously usable.
- Classify the status. Mark the figure as a measured result, a calibrated specification, a design target or a roadmap milestone. A planned capacity is not a delivered benchmark.
- Inspect error-correction behavior. Find the code or protection method, cycle count, logical error rate, code-distance trend, supported operations, decoder and feedback latency. Check whether error decreases as protection resources increase.
- Record computation size. Capture width and depth together. Note two-qubit-gate count, connectivity, routing and SWAP overhead, circuit family, number of shots and the accuracy threshold used to call the result successful.
- Examine benchmark design. Ask who selected the circuits, whether they represent an application or a synthetic workload, which compilation and mitigation methods were used, and whether uncertainty and repetitions are reported. A 2025 review in Nature Reviews Physics cautioned that benchmark quality varies and that weak benchmarks can misdirect development.
- Demand an end-to-end comparison. For an advantage claim, require a defined task, an independently validated quantum answer, a strong classical method for the same task and relevant measures such as runtime, cost, energy or accuracy. Include data movement, classical preprocessing and postprocessing, error mitigation and the quantum service’s actual execution time.
What a fair classical comparison looks like
A quantum result is meaningful only relative to a specified classical baseline. “Classically difficult” is not a sufficient description. The comparison should identify the problem size, required output precision, acceptable failure probability and the best practical classical algorithm or implementation available for that case.
A resource estimate should include logical-qubit count, logical-gate count, correction overhead, decoding work and wall-clock assumptions. AWS’s end-to-end resource-estimation guidance emphasizes calculating these quantum requirements and comparing them with classical solutions. If the quantum workflow uses a classical optimizer, sampler, tensor-network check, postselection or error-mitigation pass, those costs belong in the comparison.
IBM’s November 2025 discussion of advantage candidates said the examples it considered had not yet met its framework’s validation and measurable-separation tests at that time. That statement is dated and attributed; it should not be generalized to every later result or treated as a permanent verdict.
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| Figure | What it describes | How to read it |
|---|---|---|
| 5,000 two-qubit gate operations on 156 qubits | IBM Quantum, 2024 performance account | A company-reported demonstration. Confirm circuit definition, success threshold, compilation and whether the qubits were physical or logical. |
| More than 150,000 circuit-layer operations per second | IBM Quantum, 2024 performance account | A company-reported CLOPS result for the stated protocol; it is a speed metric, not proof of application advantage. |
| 200 qubits and 100 million gates | IBM April 2025 roadmap target for the planned Starling system | A future company plan, not a delivered result. IBM’s hardware page lists delivery as planned for 2029. |
These figures are not one common score. The first concerns circuit execution on a specified device, the second concerns throughput, and the third is a roadmap objective. They cannot be ranked without a shared workload, protocol and success criterion.
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Comparison framework for two or more systems
| Axis | Questions to answer |
|---|---|
| Scale unit | How many physical and logical qubits, modules and gates are available simultaneously? |
| Reliability | What are the physical gate and readout errors, logical error rates, suppression trends, drift and calibration stability? |
| Computational capability | Which logical operations are supported, what connectivity exists and how much routing overhead is required? |
| Speed | What are gate, circuit, decoding and feedback latencies, and what workload throughput was measured? |
| Error-correction maturity | Are repeated cycles, code family and distance, logical operations, decoding and feed-forward demonstrated? |
| System growth | Can wiring, electronics, packaging, cryogenics, interconnects, footprint and power scale with added capacity? |
| Application relevance | Is there a defined workload, required precision, end-to-end resource estimate and strong classical baseline? |
| Evidence quality | Are date, protocol, repetitions, uncertainty, success threshold and independent reproducibility disclosed? |
Common mistakes when reading scale claims
Equating the biggest qubit number with the best computer
Qubit totals omit error rates, connectivity, calibration availability and logical protection. Compare simultaneously usable capacity and demonstrated computation instead.
Mixing physical and logical qubits
Never place a physical-qubit headline beside a logical-qubit headline in a ranking table without labeling the units. Their resource meanings differ fundamentally.
Calling a roadmap a result
Future dates and target capacities describe intent. Put the announcement date and planned delivery date beside the target, then verify whether a measured system has since replaced it.
Treating one benchmark as universal
CLOPS, Quantum Volume, circuit depth and logical error suppression measure different properties. A strong score on one does not establish all six scalable-architecture criteria.
Ignoring classical assistance
Compilation, mitigation, decoding, optimization and validation can dominate an experiment. Report them as part of the workflow rather than presenting only quantum-chip time.
Omitting uncertainty and reproducibility
A selected best run, an average over all qubits and an independently reproduced result answer different questions. Require sample counts, uncertainty and the conditions under which the number was obtained.
A practical checklist for readers
- What exactly is being counted, and are the units physical, logical or operational?
- How many qubits were usable at the same time?
- Was the number measured, specified, simulated or planned?
- What error-correction code, cycle count and logical error trend were shown?
- Which logical gates, measurements and adaptive operations were demonstrated?
- What are the circuit width, depth, gate definition, routing overhead and success threshold?
- Which benchmark protocol and software version produced the score?
- How many runs and shots were used, and what uncertainty is reported?
- What classical preprocessing, decoding, mitigation and postprocessing were included?
- What is the strongest classical baseline for the same task and output quality?
- Can the control, cooling, packaging, interconnects, software and decoder expand with the processor?
- Is the claimed advantage a measured result or a roadmap ambition?
The most defensible scale claim is therefore multidimensional: it connects logical capacity, sustained error correction, useful circuit size, execution and feedback speed, system engineering and a fair end-to-end comparison. Until those pieces are reported together, a larger qubit count is evidence of a larger device—not necessarily a more scalable quantum computer.
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